SDI II Intel® Cyclone 10 GX FPGA IP Design Example User Guide

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ID 683815
Date 10/08/2021
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Document Table of Contents
Document Table of Contents x
1. SDI II Intel FPGA IP Design Example Quick Start Guide 2. SDI II Intel FPGA IP Design Example Detailed Description 3. SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. SDI II Intel FPGA Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Connection and Settings Guidelines 1.5.2. Design Considerations
2. SDI II Intel FPGA IP Design Example Detailed Description x
2.1. Parallel Loopback Design Examples 2.2. Serial Loopback Design Examples 2.3. Design Components 2.4. Clocking Scheme Signals 2.5. Interface Signals 2.6. Video Pattern Generator Parameters 2.7. Hardware Setup 2.8. Simulation Testbench
1. SDI II Intel FPGA IP Design Example Quick Start Guide
2. SDI II Intel FPGA IP Design Example Detailed Description
3. SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

1.5.1. Connection and Settings Guidelines

Before programing with the .sof file, ensure that the connections and settings are correct.
  • For parallel loopback design, the on-board BNC RX connector (J1/12G In) connects to an external video source and the on-board BNC TX connector (J2/12G Out) connects to a video analyzer.
  • For serial loopback design, the on-board BNC TX connector (J2/12G Out) connects to an on-board BNC RX connector (J1/12G In) or a video analyzer.
  • Ensure all switches on the development board are in default position.
  • The SDI video analyzer displays the video generated from the source.
    Note: For parallel loopback designs, change the jumper (J8) position before switching between fractional frame rate and integer frame rate video formats. Press the push button (PB1) to trigger a device (LMK03328) power cycling through the PDN pin every time you change the jumper (J8) position.
Table 4.  SW2 DIP Switch Default Settings (Bottom of the Board)
Switch Board Label Description
1 CLKBUF_SEL

Set the input source of Si53307(U7):

  • 0: Use CLKIN0 (default)
  • 1: Use CLKIN1
2 Si570_OE

Enable the output of Si570 (Y2):

  • 0: Output disabled
  • 1: Output enabled (default)
Table 5.  SW3 DIP Switch Default Settings (Bottom of the Board)
Switch Board Label Description
1 Si5340_INSEL0
  • Si5340_INSEL1, Si5340_INSEL0 = [0,0]

    Use crystal as PLL input for Si5332 (default)

  • Si5340_INSEL1, Si5340_INSEL0 = [1,0]

    Use external SMB as PLL input for Si5332

2 Si5340_INSEL1
Figure 7. Jumper Settings on Nextera 12G-SDI FMC Daughter CardRefer to these settings to change the jumper (J8) position.
Table 6.  Jumper Settings
Jumper Block Description
J7 Programming header
J8 To switch the generated clock frequency for the TX channel:
  • Pin 1–2 = 297 MHz
  • Pin 2–3 = 297/1.001 MHz
J9 To select SDI or IP mode:
  • Pin 1–2 = SDI mode
  • Pin 2–3 = IP mode
Related Information
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