CORDIC Intel® FPGA IP User Guide

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ID 683808
Date 10/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. CORDIC IP User Guide
1. CORDIC IP User Guide x
1.1. CORDIC IP Features 1.2. CORDIC IP Device Support 1.3. CORDIC IP Functional Description 1.4. CORDIC IP Parameters 1.5. CORDIC IP Signals 1.6. Document Revision History for the CORDIC Intel FPGA IP User Guide
1.3. CORDIC IP Functional Description x
1.3.1. SinCos Function 1.3.2. Atan2 Function 1.3.3. Vector Translate Function 1.3.4. Vector Rotate Function
1. CORDIC IP User Guide

1.5. CORDIC IP Signals

Table 6.  Common Signals
Name Type Description
clk Input Clock.
en Input Enable. Only available when you turn on Generate an enable port.
areset Input

Active-high reset. Asynchronous for Arria 10 and Cyclone 10 GX devices; synchronous for Agilex devices.

For asynchronous reset, deassert the reset signal synchronously to the input clock to avoid metastability issues.

For synchronous reset, minimizing resets, whenever functionally safe, gives better performance. Synchronous reset may connect to all of the design, some of the design, or none of the design at all.

Valid data is available at the the output L cycles after deasserting reset where L is the latency of the IP.

Table 7.  Sin Cos Function Signals
Name Type Configuration Range Description
a Input Signed input [− π,+π] Specifies the number of fractional bits (F IN ). The total width of this input is F IN+3.Two extra bits are for the range (representing π) and one bit for the sign. Provide the input in two’s complement form.
Unsigned input [0,+π /2] Specifies the number of fractional bits (F IN). The total width of this input is w IN=F IN+1. The one extra bit accounts for the range (required to represent π/2).
s, c Output Signed output [−1,1] Computes sin(a) and cos(a) on a user-specified output fraction width(F). The output has width w OUT= F OUT+2 and is signed and uses two's complement representation.
Unsigned output [0,1] Computes sin(a) and cos(a) on a user-specified output fraction width(F OUT). The output has the width w OUT= F OUT+1 and is unsigned.
Table 8.  Atan2 Function Signals
Name Type Configuration Range Details
x, y Input Signed input Given by w, F Specifies the total width (w) and number fractional bits (F) of the input. Provide the inputs in two’s complement form.
Unsigned input Specifies the total width (w) and number fractional bits (F) of the input.
a Output Signed output [− π,+π] Computes atan2(y,x) on a user-specified output fraction width (F). The output has the width w OUT= F OUT+3 and is signed and two's complement.
Unsigned output [0,+π /2] Computes atan2(y,x) on output fraction width (F OUT). The output format has the width w OUT = F OUT+2 and is signed. However, the output value is unsigned.
Table 9.  Vector Translate Functions Signals
Name Direction Configuration Range Details
x, y Input Signed input Given by w, F Specifies the total width (w) and number fractional bits (F) of the input. Provide the inputs in two’s complement form.
q Output Signed output [− π,+π]

Computes atan2(y,x) on a user-specified output fraction width F q . The output has the width w q =F q +3 and is signed and uses two's complement representation.

r Unsigned output Given by w, F

Computes K (x 2+y 2)0.5.

The total width of the output is w r =F q +3, or w r =F q +2 with scale factor compensation.

The number of meaningful bits depends on the number of iterations which depends on F q . The format of the output depends on the input format.

MSB(M OUT)=MSBIN+2, or MSB(M OUT)=MSBIN+1 with scale factor compensation

x, y Input Unsigned input Given by w,F Specifies the total width (w) and number fractional bits (F) of the input.
q Output Signed output [0,+π /2]

Computes atan2(y,x) on an output fraction width F q . The output has the width w q =F q +2 and is signed and uses two's complement representation.

r Unsigned output Given by w,F Computes K( x 2+y 2)0.5.

The total width of the output is w r =F q +3, or w r =F q +2 with scale factor compensation.

MSB(M OUT)=MSBIN+2, or MSB(M OUT)=MSBIN+1 with scale factor compensation.

Table 10.  Vector Rotate Function Signals
Name Direction Configuration Range Details
x, y Input Signed input [−1,1] Specifies the fraction width (F), total number of bits is w = F+2. Provide the inputs in two’s complement form.
a Input Signed input [− π,+π] Number of fractional bits is F (provided previously for x and y), total width is w a = F+3.
x0, y0 Output Signed output [−20.5 ,+20.5]K Number of fractional bits F OUT, where w OUT = FOUT +3 or w OUT = FOUT +2 with scale factor reduction.
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