CORDIC Intel® FPGA IP User Guide

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ID 683808
Date 10/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. CORDIC IP User Guide
1. CORDIC IP User Guide x
1.1. CORDIC IP Features 1.2. CORDIC IP Device Support 1.3. CORDIC IP Functional Description 1.4. CORDIC IP Parameters 1.5. CORDIC IP Signals 1.6. Document Revision History for the CORDIC Intel FPGA IP User Guide
1.3. CORDIC IP Functional Description x
1.3.1. SinCos Function 1.3.2. Atan2 Function 1.3.3. Vector Translate Function 1.3.4. Vector Rotate Function
1. CORDIC IP User Guide

1.4. CORDIC IP Parameters

Table 2.  SinCos Parameters
Parameter Values Description
Input data widths
Fraction F 1 to 64 Number of fraction bits.
Width w Derived Width of fixed-point data.
Sign signed or unsigned The sign of the fixed-point data.
Output data widths
Fraction 1 to 64, where F OUT ≤ F IN Number of fraction bits.
Width Derived Width of fixed-point data.
Sign Derived The sign of the fixed-point data.
Generate enable port On or off Turn on for enable signal.
Table 3.  Atan2 Parameters
Parameter Values Description
Input data widths
Fraction 1 to 64 Number of fraction bits.
Width 3 to 64 Width of fixed-point data.
Sign signed or unsigned The sign of the fixed-point data.
Output data widths
Fraction   Number of fraction bits.
Width Derived Width of fixed-point data.
Sign Derived The sign of the fixed-point data.
Generate enable port On or off Turn on for enable signal.
LUT Size Optimization On or off Turn on to move some of the typical CORDIC operations into look up tables to reduce implementation cost.
Manually Specify LUT Size On or off Turn on to input the LUT size. Larger values (9-11) enable mapping some computations to memory blocks Only when LUT Size Optimization is on.
Table 4.  Vector Translate Parameters
Parameter Values Description
Input data widths
Fraction 1 to 64 Number of fraction bits.
Width
  • signed: 4 to 64
  • unsigned: F to 65
Width of fixed-point data.
Sign signed or unsigned The sign of the fixed-point data
Output data widths
Fraction 1 to 64 Number of fraction bits.
Width Derived Width of fixed-point data.
Sgn Derived The sign of the fixed-point data
Generate enable port On or off Turn on for enable signal.
Scale factor compensation On or off

For vector translate, a CORDIC specific constant that converges to 1.6467602... scales the magnitude of the vector (x2+y2)0.5 so that the value for the magnitude, M, is M = K(x2+y2)0.5.

The format of the output depends on the input format. The largest output value occurs when both the inputs are equal to the maximum representable input value, j.

In this context:

M = K(j 2+j 2)0.5

= K(2j 2)0.5

= K20.5(j 2)0.5

= K 20.5 j

= 2.32j

Therefore, two extra bits left of the MSB of j are required to ensure M is representable. If scale factor compensation is selected, M becomes: M = j0.5 ~ 1.41 j

One extra bit is sufficient for representing the range of M.

Scale factor compensation affects the total width of the output.
Table 5.  Vector Rotate Parameters
Parameter Values Description
Input data widths
X,Y inputs
Fraction 1 to 64 Number of fraction bits.
Width Derived Width of fixed-point data.
Sign signed The sign of the fixed-point data.
Angle input
Fraction Derived -
Width Derived -
Sign Derived -
Output data widths
Fraction 1 to 64 Number of fraction bits.
Width Derived Width of fixed-point data.
Sign Derived The sign of the fixed-point data
Generate enable port On or off Turn on for enable signal.
Scale factor compensation On or off

Turn on to compensate the CORDIC-specific constant on the magnitude output. For both signed and unsigned inputs, turning on decreases by 1 the weight of the magnitude for x0 and y0. The outputs belong to the interval [-20.5, +20.5]K. Under default settings, the output interval will therefore be [-20.5K , +20.5K] (with K~1.6467602...), or ~[-2.32, +2.32]. Representing the values in this interval requires 3 bits left of the binary point, one of which is for the sign. When you turn on Scale factor compensation, the output interval becomes [-20.5, +20.5] or ~[-1.41, 1.41], which requires two bits left of the binary point, one of which is for the sign.

Scale factor compensation affects the total width of the output.
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