F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

5. Design Example: Multiple IP Core Instantiation

The multiple IP core design example demonstrates the ability to instantiate same F-Tile Ethernet Intel FPGA Hard IP multiple times in your design.

The number of instantiated IP instances depends on the Ethernet mode. For more details, refer to Features. To generate the design example, you must first set the parameter values for the IP core variation you intend to generate in your end product. Generating the design example creates multiple copies of your IP core; the testbench design example uses this variation as the DUT. If your parameter values for the DUT don't match the parameter values in your end product, the design example you generate does not exercise the IP core variation you intend.

The multi IP core design example supports PTP feature for FGT PMA type.

The following IP parameter settings were used to generate this design example:
Table 12.  IP Parameters for 25G Ethernet Mode with 1 Lane Design ExampleTable specifies parameter settings used to generate this design example.
Selected IP Parameter Settings Value
IP Tab: General Options
PMA type FGT
Ethernet mode 25GE-1
Client interface MAC segmented
FEC mode

IEEE 802.3 RS(528,514) (CL91)
PMA reference frequency 156.25
System PLL frequency 805.664062
Example Design Tab: Available Example Designs
Select Design Multi instance of IP core

For more information about steps on how to generate a design example, refer to the Generating the Design Example.


Section Content
Features
Functional Description
Simulation

Related Information
Level Two Title