6.6. Sink Deep Color Implementation When Support FRL = 1

HDMI Intel® FPGA IP User Guide

Download PDF

ID 683798

Date 3/03/2023

Version

Public

A newer version of this document is available. Customers should click here to go to the newest version.

Visible to Intel only — GUID: pxm1568793820677

Ixiasoft

View Details

6.6. Sink Deep Color Implementation When Support FRL = 1

When Support FRL = 1, you should drive vid_clk based on their frequency, regardless of the color depth ratio.

vid_clk frequency = 225 MHz

In deep color mode, the video data (30 bpp, 36 bpp, or 48 bpp) in the vid_clk domain has higher throughput than the data in the ls_clk domain. The HDMI RX core uses the vid_valid signal to indicate the validity of the video data at a specific clock.

Figure 67. Deep Color Implementation When Support FRL = 1

If your user logic cannot process the video data at a faster rate, you can use a DCFIFO to clock cross the video data from vid_clk to the actual pixel clock as shown in the diagram below. The wren signal of the DCFIFO IP connects to the vid_valid signal from the HDMI RX core. The rden signal is always asserted.

When operating in 10 bits per color, the vid_ready signal is high for 4 out of 5 clock cycles. For every 5 clock cycles, the HDMI RX core receives 4 valid video data with 10 bits per color.

The timing diagrams and description below assume that the video data at the vid_clk domain is running at the actual deep color data rate. If the video data at the vid_clk domain is running faster than the actual deep color data rate, the vid_valid signal would toggle more.

Figure 68. 10 Bits per Component (30 Bits per Pixel)When operating in 10 bits per component, the vid_valid signal is high for 4 out of 5 clock cycles. For every 5 clock cycles, the HDMI RX core receives 4 valid video data with 10 bits per component.

Figure 69. 12 Bits per Component (36 Bits per Pixel)When operating in 12 bits per component, the vid_valid signal is high for 2 out of 3 clock cycles. For every 3 clock cycles, the HDMI RX core receives 2 valid video data with 12 bits per component.

Figure 70. 16 Bits per Component (48 Bits per Pixel)When operating in 16 bits per component, the vid_valid signal is high for 1 out of 2 clock cycles. For every 2 clock cycles, the HDMI RX core receives 1 video valid data with 16 bits per component.

Select Your Language

Using Intel.com Search

Quick Links

Recent Searches

Advanced Search

Only search in

HDMI Intel® FPGA IP User Guide

6.6. Sink Deep Color Implementation When Support FRL = 1