11. Document Revision History for the HDMI Intel® FPGA IP User Guide

HDMI Intel® FPGA IP User Guide

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Date 3/03/2023

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11. Document Revision History for the HDMI Intel® FPGA IP User Guide

Document Version	Intel® Quartus® Prime Version	IP Version	Changes
2023.03.03	22.2	19.7.0	Corrected the Oversampling Blocks and Clock Enable Block — FRL Support Turned On diagram in the Clock Enable Generator topic.
2022.07.29	22.2	19.7.0	Notification of removal of Cygwin component from the Windows* version of Nios II EDS and the requirement to install WSL for Windows* users. Updated the Resource Utilization table under the HDMI Overview section. Added the AVI version bit [121:120] to Source Auxiliary Video Information (AVI) InfoFrame for Support FRL = 1 Designs table under HDMI Source section. Added two more registers in the HDMI Source AXI2CV Register Summary table under the Registers section: 0x6B - VIDEO_MODE_HORIZONTAL_SYNC_POLARITY 0x6C - VIDEO_MODE_VERTICAL_SYNC_POLARITY Added details for registers 0x6b and 0x6C.
2022.04.22	22.1	19.7.0	Added Section: Terms and Acronyms. Updated the following tables: HDMI Intel FPGA IP Release Information. HDMI Intel FPGA IP FRL Feature Support in Intel Agilex F-tile, Intel Stratix 10, and Intel Arria 10 Devices Added label HDMI TX Core in Figure: HDMI Source Signal Flow Diagram for Support FRL = 1 Design. Added the following sections in HDMI Source: TX Core-PHY Interface AXI4 Stream to Clocked Video Converter (AXI2CV) AXI-to-Clocked Video (AXI2CV) Remap Avalon Memory-Mapped Demultiplexer HDMI TX Register HDMI TX Interrupt TX AXI4-Stream Auxiliary Bridge TX Auxiliary User Packet TX AXI4-Stream Auxiliary Arbiter TX AXI4-Stream Auxiliary Packetizer TX Avalon-ST Auxiliary Arbiter Edited Table: Source Interfaces Added axi4s_reset Port for Clock Interface Added Interface AXI4-StreamVideo (Only applicable when Enable Active Video Protocol = AXIS-VVP Full) AXI4-Stream Video (Only applicable when Enable Active Video Protocol = AXIS-VVP Full) HDMI TX Avalon Memory-Mapped Control (Only applicable when Enable Active Video Protocol = AXIS-VVP Full) Edited Table: Clock Frequencies for FRL Mode at Different Link Rates. Added label HDMI RX Core in Figure: HDMI Sink Signal Flow Diagram for Support FRL = 1 Design. Added the following sections in HDMI Sink: RX Core-PHY Interface Clocked Video to AXI4-Stream (CV2AXI) Remap Avalon Memory-Mapped Demultiplexer HDMI RX Register HDMI RX Interrupt RX AXI4-Stream Auxiliary Bridge RX Auxiliary Packet Filter RX Auxiliary User Packetizer Edited Table: Sink Interfaces AXI4-StreamVideo (Only applicable when Enable Active Video Protocol = AXIS-VVP Full) AXI4-Stream Video (Only applicable when Enable Active Video Protocol = AXIS-VVP Full) Avalon Memory-Mapped Control (Only applicable when Enable Active Video Protocol = AXIS-VVP Full) Edited section HDMI Parameters: Added Enable active video protocol in HDMI Source Parameters Added Table: Parameters when Enable Active Video Protocol is set to AXIS-VVP Full. Added Section: Registers
2021.12.15	21.4	19.6.1	Added Intel® Agilex™ F-tile device support. Added HDMI Intel Agilex F-tile FPGA IP Design Example User Guide as related information in HDMI Intel® FPGA IP Quick Reference and HDMI Hardware Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-tile Devices sections. Edited the Description for Decoder Status Port in Table: Sink Interfaces.
2021.11.12	21.3	19.6.1	Updated Table: HDCP Resource Utilization for Support HDCP Key Management = 1. Updated Table: HDMI Source Parameters and HDMI Sink Parameters for Support HDCP Key Management.
2021.08.06	21.2	19.6.1	Added the link for Intel Arria 10 HDMI 2.1 System Design Guidelines in HDMI Intel FPGA IP Quick Reference. Changed the TMDS Clock Rate (MHz) for Stratix V in Table: HDMI PLL Desired Output Frequencies for 8-bpc Video. Edited the description from HDMI 1.4b to HDMI 2.0 in Source Scramble, TMDS/TERC4 Encoder. Edited Figure: Typical Window of Opportunity for H sync to asserted when V Sync is high. Edited the Description for Encoder Control Port and I²C Master Interface Port in Table: HDMI Source Interfaces. Edited the Description for Decoder Status Port in Table: HDMI Sink Interfaces.
2021.06.25	21.2	19.6.1	Updated Table: HDMI Intel FPGA IP FRL Feature Support in Intel Stratix 10 and Intel Arria 10 Devices and added Arria 10 as Final and Stratix 10 as Preliminary for Support FRL = 1. Updated Table: HDMI Intel FPGA IP Resource Utilization and added the performance data for Intel Arria 10 (Support FRL = 1). Edited the description in Source Audio Encoder. Updated Table: HDMI Source Interfaces in Source Interfaces: Updated the Description for vid_clk Port, vid_ready Port and vid_valid Port. Edited the Clock Domain and Descriptionfor TMDS/FRL Data Port Interface. Edited the Clock Domain for Encoder Control Port Interface, PHY Interface Control Port and Hot Plug Detect. Updated Source Clock Tree: Edited the description. Added Figure: Source clock tree when Support FRL = 1. Added Figure: Source clock tree when Support FRL =0. Added Intel Stratix 10 in Link Training Procedure. Updated FRL CLocking Scheme: Updated the description and the calculation to configure `vid_clk` to the maximum frequency. Removed column ls_clk Frequency (MHz) from the Table: Clock Frequencies for FRL Mode at Different Link Rates. Updated Valid Video Data: Updated the description and Figure: Video Clock Running at Faster Frequency. Added Figure: Timing diagram for the vid_valid generation. Added topic Variable Refresh Rate(VRR) and Auto Low Latency Mode (ALLM) in HDMI Source and HDMI Sink. Removed Table: Auxiliary Packet Memory Map and Table: Packet Payload Data Byte from Sink Auxiliary Packet Capture. Updated Sink Auxiliary Data Port and added the following topics: Sink General Control Packet (GCP). Sink Auxiliary Video Information (AVI) InfoFrame Bit-Fields. Sink HDMI Vendor Specific InfoFrame (VSI). Updated Sink Audio Decoder and added the following topics:: Audio InfoFrame (AI) Bundle Bit-Fields. Audio Metadata Bundle Bit-Fields. Updated Table: Sink Interfaces in Sink Interfaces: Updated the Description for ls_clk. Edited the Clock Domain for TMDS/FRL Data Port Interface. Edited the Clock Domain for Decoder Status Port Interface. Updated Sink Clock Tree : Added Figure: Sink clock tree when Support FRL = 1. Added Figure: Sink clock tree when Support FRL = 0. Edited the description in Link Training Procedure. Updated Table: HDMI Source Parameters and HDMI Sink Parameters: Edited the description for Support Auxiliary parameter. Added the row Include I2C Master/Slave.
2021.05.12	21.1	19.6.0	Removed (Support FRL = 0 only) from Support HDCP 2.3 and Support HDCP 1.4 in Table : HDMI Source Interfaces and Table : HDMI Sink Interfaces. Added Support HDCP Key Management in Table: HDMI Source Interfaces and Table: HDMI Sink Interfaces. Added Table: Source Interfaces and Sink Interfaces: Added This signal is not available if you turn on the Support HDCP Key Management parameter under the description for Conduit (Key) port type. Changed the port name from kmem_addr to kmem_rdaddr. Changed the port name from kmem_rddata to kmem_q. Added Avalon-MM port type.
2021.04.01	21.1	19.6.0	Updated Table: Sink Interfaces: Updated the descriptions for the `scdc_frl_ltp_req` port. Edited the port name `rx_hpd` to `rx_hpd_req`, change the direction from Inout to Output and updated the descriptions. Updated Link Training Procedure. Removed Figure Link Training Pattern.
2020.12.14	20.4	19.6.0	Added support for HDMI 2.1 with fixed rate link (FRL) enabled for Intel® Stratix® 10 devices. Edited the description in the HDMI Overview section. Updated table title HDMI Intel FPGA IP FRL Feature Support in Intel® Arria® 10 Devices Feature Support Level Support FRL to HDMI Intel FPGA IP FRL Feature Support in Intel® Stratix® 10 and Intel® Arria® 10 Devices Feature Support Level Support FRL. Updated the maximum data rates for Intel® Stratix® 10 devices in Table: HDMI Data Rate. Updated the resource utilization data in Table: HDMI Intel FPGA IP Resource Utilization and Table: HDCP Resource Utilization. Updated table title Recommended Speed Grades for Intel® Arria® 10 Devices (Support FRL = 1) to Recommended Speed Grades for Intel® Stratix® 10 and Intel® Arria® 10 Devices (Support FRL = 1) and added recommended speed grades for Intel® Stratix® 10 devices. Updated the FRL Clocking Scheme section: Edited the FRL character processing description and associated figure. Added frl_clk frequency for Intel® Stratix® 10 devices in Table: Clock Frequencies for FRL Mode at Different Link Rates. Edited the minimum and maximum TX clkout frequencies for TMDS_BIT_CLOCK_RATIO = 0 in Table: Clock Frequencies for TMDS Mode at Different Link Rates. Updated the description for the `kmem_addr[3:0]`(HDCP 2.3) and `kmem_addr[9:4]` (HDCP 1.4) ports in Table: HDMI Source Interfaces. Updated Table: Sink Interfaces: Updated the descriptions for the `vid_lock` port. Edited the port name `kmem_addr[3:0]` (HDCP 2.3) to `kmem_addr[7:0]` (HDCP 2.3), and `kmem_addr[9:4]` (HDCP 1.4) to `kmem_addr[13:8]` (HDCP 1.4). Updated the description for the `kmem_rddata[31:0]` (HDCP 2.3) and `kmem_rddata[87:32]` (HDCP 1.4) ports. Edited the description in the Sink FRL Resampler section. Edited the description in the Sink Clock Tree section. Updated the following figures: HDMI Source Signal Flow Diagram for Support FRL = 1 Design HDMI Sink Signal Flow Diagram for Support FRL = 1 Design Edited the descriptions for Device family, Pixels per clock, Transceiver width, Support deep color, Support HDCP 2.3, Support HDCP 1.4, and Support FRL in Table: HDMI Source Parameters and Table: HDMI Sink Parameters. Removed the support for 4 symbols per clock feature in the HDMI Simulation Example section. Made editorial edits throughout the document.
2020.09.28	20.3	19.5.0	The FRL path now uses the transceiver recovered clock domain instead of the `ls_clk` domain. Updated the following Source sections with the transceiver recovered clock domain information. Source Functional Description Source FRL Resampler Source Clock Tree Edited the description for the `ls_clk` signal in the Source Interfaces section. Added the following signals in the Source Interfaces section. `tx_clk` `os` `mgmt_clk` `in_lock` `tx_hpd` `tx_hpd_req` `i2c_scl` `i2c_sda` `i2c_master_address[3:0]` `i2c_master_write` `i2c_master_read` `i2c_master_writedata[31:0]` `i2c_master_readdata[31:0]` `mgmt_clk` Removed the `ls_clk` domain information from the FRL Clocking Scheme section. Removed the `ls_clk` domain information and updated the block diagram and the timing diagrams with the transceiver recovered clock information in the Source Deep Color Implementation When Support FRL = 1 section. Added the following new Source sections: TX Oversampler Clock Enable Generator I²C Master Updated the following Sink sections with the transceiver recovered clock domain information. Sink Functional Description Sink FRL Resampler Sink Clock Tree Added the following new Sink sections: RX Oversampler I2C Slave EDID RAM Edited the description for the `ls_clk` signal and added information about the transceiver recovered clock, oversampling (`os`), I2C slave, and the EDID RAM signals in the Sink Interfaces section. Added a note in the description for the `mode` signal in the Sink Interfaces section. This signal is unused in FRL mode. Edited the `scdc_i2c_clk` clock domain to `i2c_clk` clock domain in the Status and Control Data Channel (SCDC) Interface and Sink Interfaces sections. Edited the typo in the color depth ratio for 8 bits per color in the Sink Deep Color Implementation When Support FRL = 0 section. The correct color depth ratio for 8 bits per color should be 1.0, not 1.6. Removed the `ls_clk` domain information and updated the block diagram and the timing diagrams with the transceiver recovered clock information in the Sink Deep Color Implementation When Support FRL = 1 section. Updated the HDMI Parameters section with the following new parameters information. Include I2C Include EDID RAM EDID RAM size RAM file path HPD polarity Added a note about the TMDS bit rate and TMDS character rate information in the PLL Intel FPGA IP Cores section.
2020.06.02	20.2	19.4.0	Updated HDCP feature support for Intel® Stratix® 10 devices. Note: The HDCP feature is not included in the Intel® Quartus® Prime Pro Edition software. To access this feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html. Updated the HDCP resource utilization data for Intel® Arria® 10 devices and added data for Intel® Stratix® 10 devices in the Resource Utilization section. Updated the HDCP 1.4 Key Port address information in HDCP 1.4 TX Architecture and HDCP 1.4 RX Architecture sections. Added information about the `reset_vid`, `hdcp1_disable`, and `hdcp2_disable` signals in the Source Interfaces section. Added information about the `reset_vid`, `streamid_type`, `hdcp1_disable`, and `hdcp2_disable` signals in the Sink Interfaces section. Added a note and edited the bit-field information in the Source HDMI Vendor Specific InfoFrame (VSI) section. For the HF-VSIF transmission, use external VSI by asserting control bit to 1 and send the data through the Auxiliary Data Port.
2020.04.13	20.1	19.4.0	Updated the data rate for Intel® Arria® 10 devices in the Resource Utilization section. Removed the HDCP Over HDMI Design Examples for Intel® Arria® 10 Devices section. This information is now available in the HDMI Intel® Arria® 10 FPGA IP Design Example User Guide. Edited the port bit in `avi[121]` to `avi[122]` in the Source Auxiliary Control Port and Source Interfaces sections. Removed the AVI version bit information and added information about setting the AVI version for Support FRL = 1 in the Source Auxiliary Video Information section. Added HDMI 2.1 Specification reference for FRL mode in the Source Audio Encoder section. Edited the description for `ls_clk`, `vid_clk`, and `frl_clk` in the Source Interfaces and Sink Interfaces sections. Edited the clocks information in the FRL Clocking Scheme section. Added the following sections for deep color implementation: Source Deep Color Implementation When Support FRL = 0 Source Deep Color Implementation When Support FRL = 1 Sink Deep Color Implementation When Support FRL = 0 Sink Deep Color Implementation When Support FRL = 1 Edited the port bit in `info_avi[120]` to `info_avi[122]` in the Sink Interfaces section. Added a note in the HDMI Simulation Example section that the simulation flow applies only for the Intel® Quartus® Prime Standard Edition software using ModelSim* - Intel® FPGA Starter Edition. For the Intel® Quartus® Prime Pro Edition simulation flow, refer to the respective design example user guides.
2020.02.10	19.4	19.3.0	Added support for HDMI 2.1 with fixed rate link (FRL) enabled. This feature is available only for Intel® Arria® 10 devices. Added information that HDMI 2.1 supports pixel frequency up to 1,118 MHz and supports only 8 bits per component in the HDMI Intel® FPGA IP Quick Reference section. Added information about FRL in the HDMI Overview section. Added information about the signal flow for Support FRL = 1 in the Source Functional Description and Sink Functional Description sections. Updated the Source Auxiliary Video Information (AVI) InfoFrame section with Support FRL = 1 information. Updated the Source Clock Tree and Sink Clock Tree sections with FRL information. Updated the Source Interfaces and Sink Interfaces sections with FRL information. Updated the HDMI Parameters section to include Support FRL parameter. Added the following new sections in the HDMI Source chapter: FRL Packetizer FRL Character Block and Super Block Mapping Reed Solomon (RS) Forward Error Correction (FEC) Generation and Insertion FRL Scrambler and Encoder Source FRL Resampler FRL Clocking Scheme Valid Video Data Source Link Training Procedure Added the following new sections in the HDMI Sink chapter: FRL Depacketizer Sink FRL Character Block and Super Block Demapper Sink FRL Descrambler and Decoder Sink FRL Resampler Sink Link Training Procedure Updated the diagrams in the Source Clock Tree and Sink Clock Tree sections.
2019.10.10	19.3	19.1.0	Added a new section about High-bandwidth Digital Content Protection (HDCP). This feature is available only for Intel® Arria® 10 devices. Note: The HDCP feature is not included in the Intel® Quartus® Prime Pro Edition software. To access this feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html. Added information about the following HDCP-related parameters in the HDMI Source Parameters and HDMI Sink Parameters sections: Support HDCP 1.4 Support HDCP 2.3 Added information about HDCP-related signals in the Source Interfaces and Sink Interfaces sections. Added information about a new design example that demonstrates the HDCP feature for Intel® Arria® 10 devices in the Intel® Quartus® Prime Pro Edition software.
2019.04.29	19.1	19.1	Added support for Intel® Stratix® 10 L-tile devices. Support for both Intel® Stratix® 10 L-tile and H-tile devices are final. Updated the support for YCbCr 4:2:2 pixel encoding in the Resource Utilization section. The HDMI IP core supports 8-bit and 10-bit color depth for YCbCr 4:2:2 pixel encoding. Added performance data for Intel® Stratix® 10 L-tile and H-tile devices, and updated the data for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices for version 19.1. Updated the description for the `locked[2:0]`, `in_lock[2:0]`, and `ctrl[N*6-1:0]` ports. Added information insertion and filtration for the control ports in the Source Auxiliary Control Port section.
2019.01.21	18.1	18.1	Added a note in the Sink Word Alignment and Channel Deskew section that the word alignment logic in the HDMI RX core is disabled for HDMI 2.0 resolution (data rate >3.4 Gbps) in Intel® Arria® 10 and Intel® Cyclone® 10 GX devices. For Intel® Stratix® 10 devices, the HDMI RX core uses a new word alignment algorithm logic to achieve fast word alignment time for HDMI 2.0 resolution (data rate >3.4Gbps). Updated the description for the `vid_lock` port to add that the IP detects HTotal, VTotal, HSync Width, VSync Width, HSync Polarity, and VSync Polarity. and a change in these parameters across two frames will deassert the `vid_lock` signal.
2018.05.07	18.0	18.0	Update the HDMI specification reference to 2.0b. The HDMI Intel® FPGA IP core now supports HDMI Specification 2.0b. Added preliminary support for Intel® Stratix® 10 (H-Tile) devices. Updated support for Intel® Cyclone® 10 GX devices to final. Clarified in the features list that HDMI IP core supports up to 32 channels in 2-channel or 8-channel layouts. Added link to the HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide. Updated all IP names as part of standardization and rebranding exercise. Removed a note that said the HDMI RX core does not support SCDC read request feature for this release. The HDMI RX core fully supports SCDC features since version 17.1. Added a note in the Sink Clock Tree section that GPLL refers to IOPLL Intel® FPGA IP for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices; PLL Intel® FPGA IP for Arria V and Stratix V devices. Edited the recommended speed grade information for Intel® Cyclone® 10 GX. The recommended speed grade is -5. Edited typo in 3D Audio Input Example figure. Changed the term Video Format to Pixel Encoding to be consistent with HDMI Specification 2.0b. Restructured the document. Placed the HDMI Hardware Design chapter after the HDMI Getting Started chapter.

Date	Version	Changes
November 2017	2017.11.06	Added advance support for Intel® Cyclone® 10 GX devices. Added resource utilization data for Intel® Cyclone® 10 GX devices. Changed bits per color (bpc) to bits per component (bpc) as stated in the HDMI Specification 2.0. Renamed HDMI IP core to HDMI Intel® FPGA IP as per Intel rebranding. Changed the term Qsys to Platform Designer. Reorganized and updated the Source Functional Description and Source Functional Description sections for better understanding. Added description for the following new bit-fields: Audio InfoFrame Bundle Bit-fields Audio Metadata Bundle Bit-Fields for Packet Header and Control Audio Metadata Bundle Bit-Fields for Packet Content When 3D_AUDIO = 1 Audio Metadata Bundle Bit-Fields for Packet Content When 3D_AUDIO = 0 Added support for up to 32 audio channels. Added support for up to 1,536 kHz audio sample frequency. Updated the 3D Audio Format section and the description for `audio_clk` that for audio channels greater than 8, do not drive `audio_clk` at actual audio sample clock. Instead drive `audio_clk` with `ls_clk` and qualify `audio_data` with `audio_de` Updated the HDMI Intel® FPGA IP Source Clock Tree and HDMI Intel® FPGA IP Sink Clock Tree sections. Updated the HDMI Intel® FPGA IP Source Parameter and HDMI Intel® FPGA IP Sink Parameter sections. Updated the HDMI Intel® FPGA IP Source Interfaces and HDMI Intel® FPGA IP Sink Interfaces sections. Updated the description for the Support for deep color parameter. The parameter is now turned on by default. Edited the HDMI Intel® FPGA IP testbench block diagram. Removed 4 symbols/clock to avoid confusion. Added a note in the HDMI Intel® FPGA IP Hardware Demonstration section that the demonstration is only applicable for Arria V and Stratix V devices. For Intel® Arria® 10 devices, refer to the HDMI Intel® FPGA IP Design Example User Guide for Intel® Arria® 10 Devices. Added a note in the Simulation Walkthrough section that the walkthrough is only applicable for Intel® Quartus® Prime Standard Edition. For Intel® Quartus® Prime Pro Edition, refer to the HDMI Intel® FPGA IP Design Example User Guide for Intel® Arria® 10 Devices. Moved information about the HDMI Intel® FPGA IP design example parameters to the HDMI Intel® FPGA IP Design Example User Guide for Intel® Arria® 10 Devices.
May 2017	2017.05.08	Rebranded as Intel. Added recommended speed grades for Intel Arria 10 devices.
December 2016	2016.12.20	Updated the HDMI IP core resource utilization table with 16.1 information. Added a note for YCbCr 4:2:2 video format that 8 and 10 bits per color use the same pixel encoding as 12 bits per color, but the valid bits are left-justified with zeros padding the bits below the least significant bit. Added information for the new Design Example parameters. Removed all Arria 10 design example related information. For more information about Arria 10 design examples, refer to the HDMI IP Core Design Example User Guide. Edited the typos in the HDMI Audio Format topic. Added information that the HDMI IP core does not support 8-channel audio. Added a new output port `version[31:0]` for HDMI source and sink.
May 2016	2016.05.02	Updated the HDMI IP core resource utilization table with 16.0 information. Added information about Audio Metadata Packet for HDMI Specification Version 2.0. Added information about new HDMI source ports: `audio_metadata[164:0]` `audio_format[4:0]` Added information about new HDMI sink ports: `audio_metadata[164:0]` `audio_format[4:0]` `vid_lock` `aux_error` Provided detailed information about the HDMI source and sink `audio_de[7:0]` port. Updated the testbench diagram and description to include audio data and auxiliary data information. Added a note for Altera PLL to place the PLL in the transmit path (`pll_hdmi_tx`) in the physical location next to the transceiver PLL. Updated the HDMI sideband signals (HDMI AVI and VSI bit-fields) with default values. Added links to archived versions of the HDMI IP Core User Guide.
November 2015	2015.11.02	Updated the HDMI IP core resource utilization table with 15.1 information. Changed instances of Quartus II to Intel® Quartus® Prime . Added full support for Arria 10 devices. Added support for new features: Deep color 8-channel audio Added the following parameters for HDMI source: Support for 8-channel audio Support for deep color Added the following parameters for HDMI sink: Support for 8-channel audio Support for deep color Manufacturer OUI Device ID String Hardware Revision Updated the following interface ports for HDMI source: Added `ctrl` port Removed `gcp_Set_AVMute` and `gcp_Clear_AVMute` ports Updated the following interface ports for HDMI sink: Added `ctrl` , `mode`, `in_5v_power`, and `in_hpd` ports Removed `gcp_Set_AVMute` and `gcp_Clear_AVMute` ports Updated the HDMI sink and source block diagrams to reflect the new features. Provided block diagrams for deep color mapping. Generalized the HDMI hardware demonstration design for all supported device families (Arria V, Stratix V, and Arria 10) with detailed description.
May 2015	2015.05.04	Updated the HDMI IP core resource utilization table with 15.0 information. Added information about 4 symbols per clock mode. Added information about Status and Control Data Channel (SCDC) for HDMI specification version 2.0. Added the following interface ports for HDMI source: `TMDS_Bit_clock_Ratio` `Scrambler_Enable` Added the `TMDS_Bit_clock_Ratio` interface port for HDMI sink. Updated the HDMI hardware demonstration design with HDMI 2.0 information. Added software process flow for the HDMI hardware demonstration.
December 2014	2014.12.15	Initial release.