6.3. Sink Clock Tree

HDMI Intel® FPGA IP User Guide

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ID 683798

Date 4/22/2022

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6.3. Sink Clock Tree

The sink core uses various clocks.

The logic clocks the transceiver data into the core using the three CDR clocks: (rx_clk[2:0]).

The TMDS and TERC4 decoding is done at the link-speed clock (ls_clk) or transceiver recovered clock when you turn on the Support FRL parameter. The sink then resamples the pixel data and presents the data at the output of the core at the video pixel clock (vid_clk).

The pixel data clock depends on the video format used (within HDMI specification).

Figure 59. Sink Clock TreeThe figure shows how the different clocks connect in the sink core.

For HDMI sink, you must instantiate three receiver channels to receive data in TMDS mode or four receiver channels to receive data in FRL mode.

Figure 60. Sink Clock Tree when Support FRL = 1

When Support FRL = 1, the transceiver RX CDR has two reference clocks:

Reference clock 0, which is supplied with TMDS clock from the HDMI connector.
Reference clock 1 supplied with free running 100 MHz clock for FRL mode.

This RX CDR switches between reference clock 0 and reference clock 1 based on TMDS or FRL mode.

A general-purpose phase-locked loop GPLL that is referenced by the transceiver output clock, is used to generate the FRL (frl_clk) clock. You can fix vid_clk at a static frequency of 225 MHz. For Support FRL =1 design, ls_clk is not required.

Figure 61. Sink Clock Tree when Support FRL = 0

When Support FRL = 0, a general purpose phase-locked loop GPLL that is referenced by the TMDS clock from the HDMI sink connector, is used to generate reference clock to the transceiver RX CDR, the link speed clock (ls_clk) and video clock (vid_clk) for the core. This GPLL switches between reference clock 0 and reference clock 1 based on TMDS or FRL mode.

For Support FRL =0 design, frl_clk is not required.

Note: GPLL refers to IOPLL Intel® FPGA IP for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-tile devices; PLL Intel® FPGA IP for Arria V and Stratix V devices.

The TMDS/FRL data clocks into the core at ls_clk (Support FRL = 0) or transceiver recovered clock (Support FRL = 1) with all channels driven by the same clock source (GPLL CLK1).
The video data clocks out from the core at vid_clk.

ls_clk, and vid_clk are derived based on the color depth, TMDS Bit clock ratio, user oversampling control bit information, and the detected Clock Channel frequency band in TMDS mode (Support FRL =0).

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6.3. Sink Clock Tree