Intel® Stratix® 10 High-Speed LVDS I/O User Guide

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ID 683792
Date 11/30/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 High-Speed LVDS I/O Overview 2. Intel® Stratix® 10 High-Speed LVDS I/O Architecture and Features 3. Stratix 10 High-Speed LVDS I/O Design Considerations 4. Intel® Stratix® 10 High-Speed LVDS I/O Implementation Guides 5. LVDS SERDES Intel® FPGA IP References 6. Intel® Stratix® 10 High-Speed LVDS I/O User Guide Archives 7. Document Revision History for the Intel® Stratix® 10 High-Speed LVDS I/O User Guide
1. Intel® Stratix® 10 High-Speed LVDS I/O Overview x
1.1. Intel® Stratix® 10 LVDS SERDES Usage Modes 1.2. Intel® Stratix® 10 LVDS Channels Support 1.3. Intel® Stratix® 10 GPIO Banks, SERDES, and DPA Locations
2. Intel® Stratix® 10 High-Speed LVDS I/O Architecture and Features x
2.1. Intel® Stratix® 10 LVDS SERDES I/O Standards Support 2.2. LVDS Transmitter Programmable I/O Features 2.3. SERDES Circuitry 2.4. Differential Transmitter in Intel® Stratix® 10 Devices 2.5. Differential Receiver in Intel® Stratix® 10 Devices
2.2. LVDS Transmitter Programmable I/O Features x
2.2.1. Programmable Pre-Emphasis 2.2.2. Programmable Differential Output Voltage
2.4. Differential Transmitter in Intel® Stratix® 10 Devices x
2.4.1. Transmitter Blocks in Intel® Stratix® 10 Devices 2.4.2. Serializer Bypass for DDR and SDR Operations
2.5. Differential Receiver in Intel® Stratix® 10 Devices x
2.5.1. Receiver Blocks in Intel® Stratix® 10 Devices 2.5.2. Receiver Modes in Intel® Stratix® 10 Devices
2.5.1. Receiver Blocks in Intel® Stratix® 10 Devices x
2.5.1.1. DPA Block 2.5.1.2. Synchronizer 2.5.1.3. Data Realignment Block (Bit Slip) 2.5.1.4. Deserializer
2.5.2. Receiver Modes in Intel® Stratix® 10 Devices x
2.5.2.1. Non-DPA Mode 2.5.2.2. DPA Mode 2.5.2.3. Soft-CDR Mode
3. Stratix 10 High-Speed LVDS I/O Design Considerations x
3.1. PLLs and Clocking for Intel® Stratix® 10 Devices 3.2. Source-Synchronous Timing Budget 3.3. Guideline: LVDS SERDES IP Core Instantiation 3.4. Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode 3.5. Guideline: LVDS Transmitters and Receivers in the Same I/O Bank 3.6. Guideline: LVDS SERDES Limitation for Intel® Stratix® 10 GX 400, SX 400, and TX 400
3.1. PLLs and Clocking for Intel® Stratix® 10 Devices x
3.1.1. Clocking Differential Transmitters 3.1.2. Clocking Differential Receivers 3.1.3. Guideline: LVDS Reference Clock Source 3.1.4. Guideline: Use PLLs in Integer PLL Mode for LVDS 3.1.5. Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only 3.1.6. Guideline: Pin Placement for Differential Channels 3.1.7. LVDS Interface with External PLL Mode
3.1.6. Guideline: Pin Placement for Differential Channels x
3.1.6.1. PLLs Driving Differential Transmitter Channels 3.1.6.2. PLLs Driving DPA-Enabled Differential Receiver Channels 3.1.6.3. PLLs Driving DPA-Enabled Differential Receiver and Transmitter Channels in LVDS Interface Spanning Multiple I/O Banks
3.1.7. LVDS Interface with External PLL Mode x
3.1.7.1. IOPLL IP Signal Interface with LVDS SERDES IP 3.1.7.2. IOPLL Parameter Values for External PLL Mode 3.1.7.3. Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
3.2. Source-Synchronous Timing Budget x
3.2.1. Differential Data Orientation 3.2.2. Differential I/O Bit Position 3.2.3. Transmitter Channel-to-Channel Skew 3.2.4. Receiver Skew Margin for Non-DPA Mode
3.2.2. Differential I/O Bit Position x
3.2.2.1. Differential Bit Naming Conventions
3.2.4. Receiver Skew Margin for Non-DPA Mode x
3.2.4.1. RSKM Equation 3.2.4.2. Example: RSKM Calculation
3.5. Guideline: LVDS Transmitters and Receivers in the Same I/O Bank x
3.5.1. Using the Duplex Feature 3.5.2. Using an External PLL
4. Intel® Stratix® 10 High-Speed LVDS I/O Implementation Guides x
4.1. LVDS SERDES Intel® FPGA IP 4.2. LVDS SERDES IP Initialization and Reset 4.3. LVDS SERDES Intel® FPGA IP Timing 4.4. LVDS SERDES Intel® FPGA IP Design Examples 4.5. IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
4.1. LVDS SERDES Intel® FPGA IP x
4.1.1. Release Information 4.1.2. LVDS SERDES Intel® FPGA IP Features 4.1.3. LVDS SERDES IP Core Functional Modes 4.1.4. LVDS SERDES IP Core Functional Description
4.1.4. LVDS SERDES IP Core Functional Description x
4.1.4.1. Serializer 4.1.4.2. DPA FIFO 4.1.4.3. Bitslip 4.1.4.4. Deserializer 4.1.4.5. Clock Phase Alignment
4.2. LVDS SERDES IP Initialization and Reset x
4.2.1. Initializing the LVDS SERDES IP in Non-DPA Mode 4.2.2. Initializing the LVDS SERDES IP in DPA Mode 4.2.3. Resetting the DPA 4.2.4. Word Boundaries Alignment
4.2.4. Word Boundaries Alignment x
4.2.4.1. Aligning Word Boundaries
4.3. LVDS SERDES Intel® FPGA IP Timing x
4.3.1. I/O Timing Analysis 4.3.2. FPGA Timing Analysis 4.3.3. Timing Analysis for the External PLL Mode 4.3.4. Timing Closure Guidelines for Internal FPGA Paths 4.3.5. Guideline: Use Clock Phase Alignment Block to Improve Timing Closure
4.3.1. I/O Timing Analysis x
4.3.1.1. Obtaining RSKM Report 4.3.1.2. Obtaining TCCS Report
4.4. LVDS SERDES Intel® FPGA IP Design Examples x
4.4.1. LVDS SERDES IP Synthesizable Intel® Quartus® Prime Design Examples 4.4.2. LVDS SERDES IP Simulation Design Example 4.4.3. Combined LVDS SERDES IP Transmitter and Receiver Design Example 4.4.4. LVDS SERDES IP Dynamic Phase Shift Design Example
4.5. IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
4.5.1. Migrating Your ALTLVDS_TX and ALTLVDS_RX IP Cores
5. LVDS SERDES Intel® FPGA IP References x
5.1. LVDS SERDES Intel® FPGA IP Parameter Settings 5.2. LVDS SERDES Intel® FPGA IP Signals 5.3. Comparison of LVDS SERDES Intel® FPGA IP with Stratix® V SERDES
5.1. LVDS SERDES Intel® FPGA IP Parameter Settings x
5.1.1. LVDS SERDES Intel® FPGA IP General Settings 5.1.2. LVDS SERDES Intel® FPGA IP PLL Settings 5.1.3. LVDS SERDES Intel® FPGA IP Receiver Settings 5.1.4. LVDS SERDES Intel® FPGA IP Transmitter Settings 5.1.5. LVDS SERDES IP Core Clock Resource Summary
5.1.3. LVDS SERDES Intel® FPGA IP Receiver Settings x
5.1.3.1. Receiver Input Clock Parameters Setup
5.1.4. LVDS SERDES Intel® FPGA IP Transmitter Settings x
5.1.4.1. Setting the Transmitter Output Clock Parameters
1. Intel® Stratix® 10 High-Speed LVDS I/O Overview
2. Intel® Stratix® 10 High-Speed LVDS I/O Architecture and Features
3. Stratix 10 High-Speed LVDS I/O Design Considerations
4. Intel® Stratix® 10 High-Speed LVDS I/O Implementation Guides
5. LVDS SERDES Intel® FPGA IP References
6. Intel® Stratix® 10 High-Speed LVDS I/O User Guide Archives
7. Document Revision History for the Intel® Stratix® 10 High-Speed LVDS I/O User Guide

5.2. LVDS SERDES Intel® FPGA IP Signals

Table 31.  Common LVDS SERDES IP TX and RX Signals
Signal Name Width Direction Type Description
inclock 1 Input Clock

PLL reference clock.
pll_areset 1 Input Reset

Active-high asynchronous reset to all blocks in LVDS SERDES IP and PLL.

pll_locked 1 Output Control

Asserts when internal PLL locks.
Table 32.   LVDS SERDES IP Core RX SignalsIn this table, N represents the LVDS interface width and the number of serial channels while J represents the SERDES factor of the interface.
Signal Name Width Direction Type Description

rx_in

N Input Data

LVDS serial input data.
rx_bitslip_reset N Input Reset Asynchronous, active-high reset to the clock-data alignment circuitry (bit slip).
rx_bitslip_ctrl N Input Control
  • Positive-edge triggered increment for bit slip circuitry.
  • Each assertion adds one bit of latency to the received bit stream.
rx_dpa_hold N Input Control
  • Asynchronous, active-high signal that prevents the DPA circuitry from switching to a new clock phase on the target channel.
    • Held high—selected channels hold their current phase setting.
    • Held low—the DPA block on selected channels monitors the phase of the incoming data stream continuously and selects a new clock phase when needed.
  • Applicable in DPA-FIFO mode only.
rx_dpa_reset N Input Reset
  • Asynchronous, active-high reset to DPA blocks.
  • Minimum pulse width: one parallel clock period.
  • Applicable in DPA-FIFO and soft-CDR modes only.
rx_fifo_reset N Input Reset
  • Asynchronous, active-high reset to FIFO block.
  • Minimum pulse width: one parallel clock period.
  • Applicable in DPA-FIFO mode only.
rx_out N×J Output Data Receiver parallel data output.
  • DPA-FIFO and non-DPA modes—synchronous to rx_coreclock.
  • Soft-CDR mode—each channel has parallel data synchronous to its rx_divfwdclk.
rx_bitslip_max N Output Control
  • Bit slip rollover signal.
  • High when the next assertion of rx_bitslip_ctrl resets the serial bit latency to 0.
rx_coreclock 1 Output Clock
  • Core clock for RX interfaces provided by the PLL.
  • Not available if you use an external PLL.
rx_divfwdclk N Output Clock

The per channel and divided clock with the ideal DPA phase.

  • This is the recovered slow clock for a given channel.
  • Applicable in soft-CDR mode only.

The rx_divfwdclk signals may not be edge-aligned with each other because each channel may have a different ideal sampling phase. Each rx_divfwdclk must drive the core logic with data from the same channel.

rx_dpa_locked N Output Control

Asserted when the DPA block selects the ideal phase.

  • Driven by the LVDS SERDES IP.
  • Asserts when the signal settles on an ideal phase for that given channel.
  • Deasserts in one of these conditions:
    • The DPA moves one phase.
    • The DPA moves two phases in the same direction.
  • Applicable in DPA-FIFO and soft-CDR modes only.

Ignore all toggling of the rx_dpa_locked signal after rx_dpa_hold asserts.

Table 33.   LVDS SERDES IP TX SignalsIn this table, N represents the LVDS interface width and the number of serial channels while J represents the SERDES factor of the interface.
Signal Name Width Direction Type Description
tx_in N×J Input Data

Parallel data from the core.

tx_out

N Output Data

LVDS serial output data.

tx_outclock

1 Output Clock
  • External reference clock (sent off-chip through the TX data path).
  • Source-synchronous with tx_out.
tx_coreclock 1 Output Clock

Drives the core logic feeding the serializer.

  • If the clock phase alignment block is off, this signal is a feedthrough of the ext_coreclock input.
  • If the clock phase alignment block is on, this signal is a phase-aligned core clock signal generated by the loaden.
Table 34.  External PLL Signals for LVDS SERDES IPFor instructions on setting the frequencies, duty cycles, and phase shifts of the required PLL clocks for external PLL mode, refer to the Clock Resource Summary tab in the IP parameter editor.
Signal Name Width Direction Type Description
ext_fclk 1 Input Clock

LVDS fast clock.

  • Used for serial data transfer.
  • Required in all modes.

For more information about connecting this port with the signal from the IOPLL Intel® FPGA IP, refer to the related information.

ext_loaden

1 Input Clock

LVDS load enable.

  • Used for parallel load.
  • Not required in RX soft-CDR mode.

For more information about connecting this port with the signal from the IOPLL IP core, refer to the related information.

ext_coreclock 1 Input Clock
  • Drives the core logic feeding the serializer (TX) or receiving from the deserializer (RX).
  • Present in RX soft-CDR mode, even though the RX core registers are clocked by rx_divfwdclk.
ext_vcoph[7:0] 8 Input Clock
  • Provides the VCO clocks to the DPA circuitry for optimal phase selection.
  • Required for RX DPA-FIFO and RX soft-CDR modes
  • Required for all supported modes if you turn on Use the CPA block for improved periphery-core timing

For more information about connecting this port with the signal from the IOPLL IP core, refer to the related information.

ext_pll_locked 1 Input Data

PLL lock signal.

  • Required for RX DPA-FIFO and RX Soft-CDR modes.
  • Required for all supported modes if you turn on Use the CPA block for improved periphery-core timing.
ext_tx_outclock_fclk 1 Input Clock

Phase-shifted version of fast clock

Required for TX outclock phase shifts that are not multiples of 180°
ext_tx_outclock_ loaden 1 Input Clock

Phase-shifted version of load_enable

Required for TX outclock phase shifts that are not multiples of 180°
Related Information
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