Intel® Stratix® 10 High-Speed LVDS I/O User Guide

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ID 683792
Date 7/13/2021
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Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 High-Speed LVDS I/O Overview 2. Intel® Stratix® 10 High-Speed LVDS I/O Architecture and Features 3. Stratix 10 High-Speed LVDS I/O Design Considerations 4. Intel® Stratix® 10 High-Speed LVDS I/O Implementation Guides 5. LVDS SERDES Intel® FPGA IP References 6. Intel® Stratix® 10 High-Speed LVDS I/O User Guide Archives 7. Document Revision History for the Intel® Stratix® 10 High-Speed LVDS I/O User Guide
1. Intel® Stratix® 10 High-Speed LVDS I/O Overview x
1.1. Intel® Stratix® 10 LVDS SERDES Usage Modes 1.2. Intel® Stratix® 10 LVDS Channels Support 1.3. Intel® Stratix® 10 GPIO Banks, SERDES, and DPA Locations
2. Intel® Stratix® 10 High-Speed LVDS I/O Architecture and Features x
2.1. Intel® Stratix® 10 LVDS SERDES I/O Standards Support 2.2. LVDS Transmitter Programmable I/O Features 2.3. SERDES Circuitry 2.4. Differential Transmitter in Intel® Stratix® 10 Devices 2.5. Differential Receiver in Intel® Stratix® 10 Devices
2.2. LVDS Transmitter Programmable I/O Features x
2.2.1. Programmable Pre-Emphasis 2.2.2. Programmable Differential Output Voltage
2.4. Differential Transmitter in Intel® Stratix® 10 Devices x
2.4.1. Transmitter Blocks in Intel® Stratix® 10 Devices 2.4.2. Serializer Bypass for DDR and SDR Operations
2.5. Differential Receiver in Intel® Stratix® 10 Devices x
2.5.1. Receiver Blocks in Intel® Stratix® 10 Devices 2.5.2. Receiver Modes in Intel® Stratix® 10 Devices
2.5.1. Receiver Blocks in Intel® Stratix® 10 Devices x
2.5.1.1. DPA Block 2.5.1.2. Synchronizer 2.5.1.3. Data Realignment Block (Bit Slip) 2.5.1.4. Deserializer
2.5.2. Receiver Modes in Intel® Stratix® 10 Devices x
2.5.2.1. Non-DPA Mode 2.5.2.2. DPA Mode 2.5.2.3. Soft-CDR Mode
3. Stratix 10 High-Speed LVDS I/O Design Considerations x
3.1. PLLs and Clocking for Intel® Stratix® 10 Devices 3.2. Source-Synchronous Timing Budget 3.3. Guideline: LVDS SERDES IP Core Instantiation 3.4. Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode 3.5. Guideline: LVDS Transmitters and Receivers in the Same I/O Bank 3.6. Guideline: LVDS SERDES Limitation for Intel® Stratix® 10 GX 400, SX 400, and TX 400
3.1. PLLs and Clocking for Intel® Stratix® 10 Devices x
3.1.1. Clocking Differential Transmitters 3.1.2. Clocking Differential Receivers 3.1.3. Guideline: LVDS Reference Clock Source 3.1.4. Guideline: Use PLLs in Integer PLL Mode for LVDS 3.1.5. Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only 3.1.6. Guideline: Pin Placement for Differential Channels 3.1.7. LVDS Interface with External PLL Mode
3.1.6. Guideline: Pin Placement for Differential Channels x
3.1.6.1. PLLs Driving Differential Transmitter Channels 3.1.6.2. PLLs Driving DPA-Enabled Differential Receiver Channels 3.1.6.3. PLLs Driving DPA-Enabled Differential Receiver and Transmitter Channels in LVDS Interface Spanning Multiple I/O Banks
3.1.7. LVDS Interface with External PLL Mode x
3.1.7.1. IOPLL IP Core Signal Interface with LVDS SERDES IP Core 3.1.7.2. IOPLL Parameter Values for External PLL Mode 3.1.7.3. Connection between IOPLL IP Core and LVDS SERDES IP Core in External PLL Mode
3.2. Source-Synchronous Timing Budget x
3.2.1. Differential Data Orientation 3.2.2. Differential I/O Bit Position 3.2.3. Transmitter Channel-to-Channel Skew 3.2.4. Receiver Skew Margin for Non-DPA Mode
3.2.2. Differential I/O Bit Position x
3.2.2.1. Differential Bit Naming Conventions
3.2.4. Receiver Skew Margin for Non-DPA Mode x
3.2.4.1. RSKM Equation 3.2.4.2. Example: RSKM Calculation
3.5. Guideline: LVDS Transmitters and Receivers in the Same I/O Bank x
3.5.1. Using the Duplex Feature 3.5.2. Using an External PLL
4. Intel® Stratix® 10 High-Speed LVDS I/O Implementation Guides x
4.1. LVDS SERDES Intel® FPGA IP 4.2. LVDS SERDES IP Core Initialization and Reset 4.3. LVDS SERDES IP Core Timing 4.4. LVDS SERDES IP Core Design Examples 4.5. IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
4.1. LVDS SERDES Intel® FPGA IP x
4.1.1. Release Information 4.1.2. LVDS SERDES IP Core Features 4.1.3. LVDS SERDES IP Core Functional Modes 4.1.4. LVDS SERDES IP Core Functional Description
4.1.4. LVDS SERDES IP Core Functional Description x
4.1.4.1. Serializer 4.1.4.2. DPA FIFO 4.1.4.3. Bitslip 4.1.4.4. Deserializer 4.1.4.5. Clock Phase Alignment
4.2. LVDS SERDES IP Core Initialization and Reset x
4.2.1. Initializing the LVDS SERDES IP Core in Non-DPA Mode 4.2.2. Initializing the LVDS SERDES IP Core in DPA Mode 4.2.3. Resetting the DPA 4.2.4. Word Boundaries Alignment
4.2.4. Word Boundaries Alignment x
4.2.4.1. Aligning Word Boundaries
4.3. LVDS SERDES IP Core Timing x
4.3.1. I/O Timing Analysis 4.3.2. FPGA Timing Analysis 4.3.3. Timing Analysis for the External PLL Mode 4.3.4. Timing Closure Guidelines for Internal FPGA Paths 4.3.5. Guideline: Use Clock Phase Alignment Block to Improve Timing Closure
4.3.1. I/O Timing Analysis x
4.3.1.1. Obtaining RSKM Report 4.3.1.2. Obtaining TCCS Report
4.4. LVDS SERDES IP Core Design Examples x
4.4.1. LVDS SERDES IP Core Synthesizable Intel® Quartus® Prime Design Examples 4.4.2. LVDS SERDES IP Core Simulation Design Example 4.4.3. Combined LVDS SERDES IP Core Transmitter and Receiver Design Example 4.4.4. LVDS SERDES IP Core Dynamic Phase Shift Design Example
4.5. IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
4.5.1. Migrating Your ALTLVDS_TX and ALTLVDS_RX IP Cores
5. LVDS SERDES Intel® FPGA IP References x
5.1. LVDS SERDES IP Core Parameter Settings 5.2. LVDS SERDES IP Core Signals 5.3. Comparison of LVDS SERDES Intel® FPGA IP with Stratix® V SERDES
5.1. LVDS SERDES IP Core Parameter Settings x
5.1.1. LVDS SERDES IP Core General Settings 5.1.2. LVDS SERDES IP Core PLL Settings 5.1.3. LVDS SERDES IP Core Receiver Settings 5.1.4. LVDS SERDES IP Core Transmitter Settings 5.1.5. LVDS SERDES IP Core Clock Resource Summary
5.1.3. LVDS SERDES IP Core Receiver Settings x
5.1.3.1. Receiver Input Clock Parameters Setup
5.1.4. LVDS SERDES IP Core Transmitter Settings x
5.1.4.1. Setting the Transmitter Output Clock Parameters
1. Intel® Stratix® 10 High-Speed LVDS I/O Overview
2. Intel® Stratix® 10 High-Speed LVDS I/O Architecture and Features
3. Stratix 10 High-Speed LVDS I/O Design Considerations
4. Intel® Stratix® 10 High-Speed LVDS I/O Implementation Guides
5. LVDS SERDES Intel® FPGA IP References
6. Intel® Stratix® 10 High-Speed LVDS I/O User Guide Archives
7. Document Revision History for the Intel® Stratix® 10 High-Speed LVDS I/O User Guide

3.2.4.1. RSKM Equation

The RSKM equation expresses the relationship between RSKM, TCCS, and SW.
Figure 29. RSKM Equation


Conventions used for the equation:

  • RSKM—the timing margin between the clock input of the receiver and the data input sampling window, and the jitter induced from core noise and I/O switching noise.
  • Time unit interval (TUI)—time period of the serial data.
  • SW—the period of time that the input data must be stable to ensure that the LVDS receiver samples the data successfully. The SW is a device property and varies according to device speed grade.
  • TCCS—the timing difference between the fastest and the slowest output edges across channels driven by the same PLL. The TCCS measurement includes the tCO variation, clock, and clock skew.
Note: If there is additional board channel-to-channel skew, consider the total receiver channel-to-channel skew (RCCS) instead of TCCS. .

You must calculate the RSKM value, based on the data rate and device, to determine if the LVDS receiver can sample the data:

  • A positive RSKM value, after deducting transmitter jitter, indicates that the LVDS receiver can sample the data properly.
  • A negative RSKM value, after deducting transmitter jitter, indicates that the LVDS receiver cannot sample the data properly.
Figure 30. Differential High-Speed Timing Diagram and Timing Budget for Non-DPA Mode This figure shows the relationship between the RSKM, TCCS, and the SW of the receiver.


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