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1. Agilex™ 7 F-Series and I-Series General-Purpose I/O Overview
2. Agilex™ 7 F-Series and I-Series GPIO Banks
3. Agilex™ 7 F-Series and I-Series HPS I/O Banks
4. Agilex™ 7 F-Series and I-Series SDM I/O Banks
5. Agilex™ 7 F-Series and I-Series I/O Troubleshooting Guidelines
6. Agilex™ 7 F-Series and I-Series General-Purpose I/O IPs
7. Programmable I/O Features Description
8. Agilex™ 7 General-Purpose I/O User Guide: F-Series and I-Series User Guide Archives
9. Documentation Related to the Agilex™ 7 General-Purpose I/O User Guide: F-Series and I-Series
10. Document Revision History for the Agilex™ 7 General-Purpose I/O User Guide: F-Series and I-Series
2.5.1. VREF Sources and VREF Pins
2.5.2. I/O Standards Implementation Based on VCCIO_PIO Voltages
2.5.3. OCT Calibration Block Requirement
2.5.4. I/O Pins Placement Requirements
2.5.5. I/O Standard Selection and I/O Bank Supply Compatibility Check
2.5.6. Simultaneous Switching Noise
2.5.7. Special Pins Requirement
2.5.8. External Memory Interface Pin Placement Requirements
2.5.9. HPS Shared I/O Requirements
2.5.10. Clocking Requirements
2.5.11. SDM Shared I/O Requirements
2.5.12. Unused Pins
2.5.13. Voltage Setting for Unused GPIO Banks
2.5.14. GPIO Pins During Power Sequencing
2.5.15. Drive Strength Requirement for GPIO Input Pins
2.5.16. Maximum DC Current Restrictions
2.5.17. 1.2 V I/O Interface Voltage Level Compatibility
2.5.18. GPIO Pins for the Avalon® Streaming Interface Configuration Scheme
2.5.19. Maximum True Differential Signaling Receiver Pairs Per I/O Lane
6.1.1. Release Information for GPIO Intel® FPGA IP
6.1.2. Generating the GPIO Intel® FPGA IP
6.1.3. GPIO Intel® FPGA IP Parameter Settings
6.1.4. GPIO Intel® FPGA IP Interface Signals
6.1.5. GPIO Intel® FPGA IP Architecture
6.1.6. Verifying Resource Utilization and Design Performance
6.1.7. GPIO Intel® FPGA IP Timing
6.1.8. GPIO Intel® FPGA IP Design Examples
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2.4.1.3. Single-Ended I/O Standards External Termination
SSTL-12, HSTL-12, POD12 I/O standards require an input VREF and a termination voltage (VTT). The reference voltage of the receiving device tracks the termination voltage of the transmitting device.
Intel recommends that you use OCT with these I/O standards to save board space and cost. OCT reduces the number of external termination resistors used.
Note: You cannot use RS and RT OCT simultaneously. For more information, refer to the related information.
I/O Standard | External Termination Scheme |
---|---|
1.2 V LVCMOS | No on-board termination required |
SSTL-12 | Single-ended SSTL I/O standard termination |
HSTL-12 | Single-ended HSTL I/O standard termination |
HSUL-12 | No on-board termination required |
POD12 | Differential POD I/O standard termination |
Differential SSTL-12 | Differential SSTL I/O standard termination |
Differential HSTL-12 | Differential HSTL I/O standard termination |
Differential HSUL-12 | No on-board termination required |
Differential POD12 | Differential POD I/O standard termination |
Figure 10. SSTL and HSTL I/O Standards External Termination
Figure 11. POD12 I/O Standard External Termination
Related Information