SmartVID Controller IP Core User Guide

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ID 683770
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. SmartVID Controller Overview 2. SmartVID Controller Getting Started 3. SmartVID Functional Description 4. SmartVID Controller Interface Signals 5. SmartVID Controller Control and Status Registers 6. SmartVID Controller Reference Design A. SmartVID Controller IP Core User Guide Archives B. Document Revision History for SmartVID Controller User Guide
2. SmartVID Controller Getting Started x
2.1. Specifying Parameters and Options 2.2. SmartVID Controller Parameters
3. SmartVID Functional Description x
3.1. SmartVID Controller Operation
5. SmartVID Controller Control and Status Registers x
5.1. VID Codes for Arria 10 Speed Grades 5.2. System Power-On
1. SmartVID Controller Overview
2. SmartVID Controller Getting Started
3. SmartVID Functional Description
4. SmartVID Controller Interface Signals
5. SmartVID Controller Control and Status Registers
6. SmartVID Controller Reference Design
A. SmartVID Controller IP Core User Guide Archives
B. Document Revision History for SmartVID Controller User Guide

6. SmartVID Controller Reference Design

The SmartVID Controller reference design provides you an overview of the SmartVID controller system.
Figure 4. SmartVID Controller System with Arria 10 DeviceThe figure below shows the system-level block diagram of the SmartVID controller with the interfacing sub-systems within an Arria 10 device.

The SmartVID controller reference design contains the following components:
  • Reset synchronizer
  • Voltage regulator
    • Designed to remap the VID code from the SmartVID controller IP core to the corresponding voltage code of the targeted voltage regulator.
  • Temperature sensor
  • JTAG block
  • IOPLL
    • The reference design uses an IOPLL to generate the required 125 MHz and 25 MHz clocks. These clocks can also be supplied by a customer design if the reference design is used as a template to add the SmartVID feature.
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