Visible to Intel only — GUID: sam1394618636209
Ixiasoft
1. Intel® MAX® 10 High-Speed LVDS I/O Overview
2. Intel® MAX® 10 High-Speed LVDS Architecture and Features
3. Intel® MAX® 10 LVDS Transmitter Design
4. Intel® MAX® 10 LVDS Receiver Design
5. Intel® MAX® 10 LVDS Transmitter and Receiver Design
6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations
7. Soft LVDS Intel® FPGA IP Core References
8. Intel® MAX® 10 High-Speed LVDS I/O User Guide Archives
9. Document Revision History for Intel® MAX® 10 High-Speed LVDS I/O User Guide
Visible to Intel only — GUID: sam1394618636209
Ixiasoft
4.1.1. Soft Deserializer
The soft deserializer converts a 1-bit serial data stream into a parallel data stream based on the deserialization factor.
Figure 15. LVDS x8 Deserializer Waveform
Signal | Description |
---|---|
rx_in | LVDS data stream, input to the Soft LVDS channel. |
fclk | Clock used for receiver. |
loaden | Enable signal for deserialization generated by the Soft LVDS IP core. |
rx_out[9:0] | Deserialized data. |