Intel® MAX® 10 High-Speed LVDS I/O User Guide

Download PDF
ID 683760
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 High-Speed LVDS I/O Overview 2. Intel® MAX® 10 High-Speed LVDS Architecture and Features 3. Intel® MAX® 10 LVDS Transmitter Design 4. Intel® MAX® 10 LVDS Receiver Design 5. Intel® MAX® 10 LVDS Transmitter and Receiver Design 6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations 7. Soft LVDS Intel® FPGA IP Core References 8. Intel® MAX® 10 High-Speed LVDS I/O User Guide Archives 9. Document Revision History for Intel® MAX® 10 High-Speed LVDS I/O User Guide
1. Intel® MAX® 10 High-Speed LVDS I/O Overview x
1.1. Soft LVDS Implementation Overview
2. Intel® MAX® 10 High-Speed LVDS Architecture and Features x
2.1. Intel® MAX® 10 LVDS Channels Support 2.2. Intel® MAX® 10 LVDS SERDES I/O Standards Support 2.3. Intel® MAX® 10 High-Speed LVDS Circuitry 2.4. Intel® MAX® 10 High-Speed LVDS I/O Location 2.5. Differential I/O Pins in Low Speed Region
3. Intel® MAX® 10 LVDS Transmitter Design x
3.1. High-Speed I/O Transmitter Circuitry 3.2. LVDS Transmitter Programmable I/O Features 3.3. LVDS Transmitter I/O Termination Schemes 3.4. LVDS Transmitter FPGA Design Implementation 3.5. LVDS Transmitter Debug and Troubleshooting
3.2. LVDS Transmitter Programmable I/O Features x
3.2.1. Programmable Pre-Emphasis 3.2.2. Programmable Differential Output Voltage
3.3. LVDS Transmitter I/O Termination Schemes x
3.3.1. Emulated LVDS External Termination 3.3.2. Sub-LVDS Transmitter External Termination 3.3.3. SLVS Transmitter External Termination 3.3.4. Emulated RSDS, Emulated Mini-LVDS, and Emulated PPDS Transmitter External Termination
3.4. LVDS Transmitter FPGA Design Implementation x
3.4.1. Soft LVDS IP Core in Transmitter Mode 3.4.2. High-Speed I/O Timing Budget 3.4.3. Guidelines: LVDS Transmitter Channels Placement 3.4.4. Guidelines: LVDS Channels PLL Placement 3.4.5. Guidelines: LVDS Transmitter Logic Placement 3.4.6. Guidelines: Enable LVDS Pre-Emphasis for E144 Package
3.4.1. Soft LVDS IP Core in Transmitter Mode x
3.4.1.1. PLL Source Selection for Soft LVDS IP Core 3.4.1.2. Guidelines: LVDS TX Interface Using External PLL 3.4.1.3. Initializing the Soft LVDS IP Core
3.4.1.1. PLL Source Selection for Soft LVDS IP Core x
3.4.1.1.1. Instantiate Soft LVDS IP Core with Internal PLL 3.4.1.1.2. Instantiate Soft LVDS IP Core with External PLL
3.4.1.2. Guidelines: LVDS TX Interface Using External PLL x
3.4.1.2.1. ALTPLL Signal Interface with Soft LVDS Transmitter 3.4.1.2.24.3.1.2.2. Determining External PLL Clock Parameters for Soft LVDS Receiver3.4.1.2.24.3.1.2.2. Determining External PLL Clock Parameters for Soft LVDS Receiver
3.4.2. High-Speed I/O Timing Budget x
3.4.2.1. Transmitter Channel-to-Channel Skew
3.5. LVDS Transmitter Debug and Troubleshooting x
3.5.1. Perform RTL Simulation Before Hardware Debug 3.5.2. Geometry-Based and Physics-Based I/O Rules
4. Intel® MAX® 10 LVDS Receiver Design x
4.1. High-Speed I/O Receiver Circuitry 4.2. LVDS Receiver I/O Termination Schemes 4.3. LVDS Receiver FPGA Design Implementation 4.4. LVDS Receiver Debug and Troubleshooting
4.1. High-Speed I/O Receiver Circuitry x
4.1.1. Soft Deserializer 4.1.2. Data Realignment Block (Bit Slip)
4.2. LVDS Receiver I/O Termination Schemes x
4.2.1. LVDS, 1.8 V LVDS, Mini-LVDS, and RSDS Receiver External Termination 4.2.2. SLVS Receiver External Termination 4.2.3. Sub-LVDS Receiver External Termination 4.2.4. TMDS Receiver External Termination 4.2.5. HiSpi Receiver External Termination 4.2.6. LVPECL External Termination
4.3. LVDS Receiver FPGA Design Implementation x
4.3.1. Soft LVDS IP Core in Receiver Mode 4.3.2. High-Speed I/O Timing Budget 4.3.3. Guidelines: Floating LVDS Input Pins 4.3.4. Guidelines: LVDS Receiver Channels Placement 4.3.5. Guidelines: LVDS Channels PLL Placement 4.3.6. Guidelines: LVDS Receiver Logic Placement
4.3.1. Soft LVDS IP Core in Receiver Mode x
4.3.1.1. PLL Source Selection for Soft LVDS IP Core 4.3.1.2. Guidelines: LVDS RX Interface Using External PLL 4.3.1.3. Initializing the Soft LVDS IP Core 4.3.1.4. Guidelines: Applying Input Delay Constraint for LVDS SERDES Receiver
4.3.1.1. PLL Source Selection for Soft LVDS IP Core x
4.3.1.1.1. Instantiate Soft LVDS IP Core with Internal PLL 4.3.1.1.2. Instantiate Soft LVDS IP Core with External PLL
4.3.1.2. Guidelines: LVDS RX Interface Using External PLL x
4.3.1.2.1. ALTPLL Signal Interface with Soft LVDS Receiver 3.4.1.2.24.3.1.2.2. Determining External PLL Clock Parameters for Soft LVDS Receiver3.4.1.2.24.3.1.2.2. Determining External PLL Clock Parameters for Soft LVDS Receiver
4.3.2. High-Speed I/O Timing Budget x
4.3.2.1. Receiver Input Skew Margin 4.3.2.2. Guidelines: LVDS Receiver Timing Constraints
4.3.2.1. Receiver Input Skew Margin x
4.3.2.1.1. RSKM Equation 4.3.2.1.2. Example: RSKM Calculation
4.4. LVDS Receiver Debug and Troubleshooting x
4.4.1. Perform RTL Simulation Before Hardware Debug 4.4.2. Geometry-Based and Physics-Based I/O Rules
5. Intel® MAX® 10 LVDS Transmitter and Receiver Design x
5.1. Transmitter–Receiver Interfacing 5.2. LVDS Transmitter and Receiver FPGA Design Implementation 5.3. LVDS Transmitter and Receiver Debug and Troubleshooting
5.2. LVDS Transmitter and Receiver FPGA Design Implementation x
5.2.1. LVDS Transmitter and Receiver PLL Sharing Implementation 5.2.2. Initializing the Soft LVDS IP Core
5.3. LVDS Transmitter and Receiver Debug and Troubleshooting x
5.3.1. Perform RTL Simulation Before Hardware Debug 5.3.2. Geometry-Based and Physics-Based I/O Rules
6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations x
6.1. Guidelines: Improve Signal Quality 6.2. Guidelines: Control Channel-to-Channel Skew 6.3. Guidelines: Determine Board Design Constraints 6.4. Guidelines: Perform Board Level Simulations
7. Soft LVDS Intel® FPGA IP Core References x
7.1. Soft LVDS Intel® FPGA IP Parameter Settings 7.2. Soft LVDS Intel® FPGA IP Interface Signals
1. Intel® MAX® 10 High-Speed LVDS I/O Overview
2. Intel® MAX® 10 High-Speed LVDS Architecture and Features
3. Intel® MAX® 10 LVDS Transmitter Design
4. Intel® MAX® 10 LVDS Receiver Design
5. Intel® MAX® 10 LVDS Transmitter and Receiver Design
6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations
7. Soft LVDS Intel® FPGA IP Core References
8. Intel® MAX® 10 High-Speed LVDS I/O User Guide Archives
9. Document Revision History for Intel® MAX® 10 High-Speed LVDS I/O User Guide

9. Document Revision History for Intel® MAX® 10 High-Speed LVDS I/O User Guide

Document Version Intel® Quartus® Prime Version Changes
2023.10.02 22.1 Added the Guidelines: Applying Input Delay Constraint for LVDS SERDES Receiver section.
2022.10.31 22.1
  • Updated the figures showing the LVDS support in I/O banks.
  • Added 1.8 V LVDS I/O standard support.
2021.11.01 21.1
  • Added 10M08 V81 package and 10M16 Y180 package for single supply devices in the LVDS Buffers in Intel® MAX® 10 Devices table.
  • Updated figure title to LVDS Support in I/O Banks of 10M02 (Single Power Supply U324 Package), 10M04, and 10M08 (Except V81, M153, and U169 Packages) Devices.
  • Added diagram: LVDS Support in I/O Banks of 10M08 V81, M153, and U169 Packages Devices.
Date Version Changes
December 2017 2017.12.15
  • Added short descriptions about the true and emulated LVDS buffers.
  • Added single power supply U324 package.
  • Updated the topic about using the Soft LVDS IP core (receiver) in external PLL mode to remove the ALTPLL IP core slow clock output (c1) connection to the Soft LVDS rx_synclock input for even deserialization factor. The rx_synclock is not used by the Soft LVDS IP core when the deserialization factor is even.
  • Updated the section about high-speed I/O timing budget:
    • Updated the high-speed I/O timing budget topic to clarify that Intel® MAX® 10 devices implements SERDES in LEs.
    • Removed information about obtaining RSKM report in the Intel® Quartus® Prime software. The software does not support generating RSKM report for Intel® MAX® 10 devices.
    • Removed the topic about assigning input delay to the LVDS receiver.
    • Added link to timing constraints section of the Intel Quartus Prime Standard Edition Handbook Volume 3: Verification.
  • Updated the condition and description for the Enable pll_areset port parameter to specify that it is not available in external PLL mode.
  • Throughout the document, added links to related information to improve usability.
  • Further edits for Intel rebranding.
February 2017 2017.02.21 Rebranded as Intel.
October 2016 2016.10.31
  • Added related information links in the topic about LVDS channels support.
  • Restructured and updated the topic about the RSKM.
  • Added a topic that describes how to assign input delay to the LVDS receiver using the Timing Analyzer.
May 2016 2016.05.02
  • Added true RSDS and emulated RSDS (three resistors) transmitter support for single supply Intel® MAX® 10 devices.
  • Updated the transmitter and receiver channels placement topics to describe about minimizing skew when you group LVDS channels for an application.
  • Updated the description of the rx_data_reset interface signal to specify that you must externally synchronize it with the fast clock.
  • Updated the General tab of the Soft LVDS parameter settings:
    • Added the Power Supply Mode option.
    • Updated the allowed values of the SERDES factor parameter.
November 2015 2015.11.02
  • Updated the high-speed LVDS circuitry figure to correct the flow from C1 in ALTPLL to inclock of ALTERA_SOFT_LVDS. Previously, the figure shows a bidirectional flow.
  • Updated the steps for determining the external PLL clock parameters for the receiver to clarify the clock names listed by the Intel® Quartus® Prime compilation report.
  • Updated the topic about Soft LVDS parameter settings:
    • Added links to topics about PLL and high-speed I/O performance in the device datasheet.
    • Corrected the conditions required to use the Enable tx_data_reset port and Enable rx_data_reset port parameters. You must turn on the Use external PLL option first.
    • Updated the allowed values for the Tx_outclock division factor and Outclock duty cycle parameters.
    • Updated the condition for the Desired transmitter outclock phase shift parameter.
  • Removed the topics about generating IP cores and the files generated by the IP core, and added a link to Introduction to Altera IP Cores.
  • Removed the statement about getting TCCS value from the Intel® Quartus® Prime compilation report. You can get TCCS value from the device datasheet.
  • Added guidelines topic about enabling LVDS pre-emphasis for Intel® MAX® 10 devices in the E144 package.
  • Updated the guidelines to control channel-to-channel skew to remove statements about getting the trace delay amount from the Fitter Report panel.
  • Added link to video that demonstrates how to generate IBIS file using the Intel® Quartus® Prime software.
  • Changed instances of Quartus II to Quartus Prime.
May 2015 2015.05.04
  • Removed the F672 package from the 10M25 device.
  • Updated the number of bottom true receiver channels for package M153 of the 10M02 device from 49 to 13.
  • Added BLVDS output support in single-supply Intel® MAX® 10 devices. Previously, BLVDS support for single-supply devices was input only.
  • Updated the RSKM definition in the topic about receiver input skew margin to include jitter induced from core noise and I/O switching noise.
  • Updated topics related to using the Soft LVDS IP core (transmitter or receiver) in external PLL mode:
    • Added rx_readclock, rx_syncclock, and tx_synclock ports.
    • Removed pll_areset port.
    • Added examples for odd and even serialization factors.
    • Added procedures to obtain the external PLL clock parameters.
    • Removed similar guidelines in the chapter for the transmitter and receiver design. The updated guidelines for the receiver only and transmitter only designs can apply for designs that use both transmitters and receivers.
  • Updated parameter settings of the Soft LVDS IP core:
    • Removed allowed values "6" and "9" from the SERDES factor parameter.
    • Added allowed value "Off" to the Enable pll_areset port parameter.
    • Updated the parameter label Register_rx_bitslip_ctrl port to Add extra register for rx_data_align port and specified that you must pre-register the port if you turn it on.
December 2014 2014.12.15
  • Updated table listing LVDS channels to include LVDS channel counts for each device package.
  • Added information in the topics about channels placement that Intel® MAX® 10 devices support x18 bundling mode.
  • Updated the examples in topics about channels PLL placement to provide more details.
  • Added link to the MAX 10 Clocking and PLL User Guide that provides more information about the PLL and the PLL output counters used to clock the soft SERDES.
September 2014 2014.09.22 Initial release.
Level Two Title