Intel® MAX® 10 High-Speed LVDS I/O User Guide

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ID 683760
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 High-Speed LVDS I/O Overview 2. Intel® MAX® 10 High-Speed LVDS Architecture and Features 3. Intel® MAX® 10 LVDS Transmitter Design 4. Intel® MAX® 10 LVDS Receiver Design 5. Intel® MAX® 10 LVDS Transmitter and Receiver Design 6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations 7. Soft LVDS Intel® FPGA IP Core References 8. Intel® MAX® 10 High-Speed LVDS I/O User Guide Archives 9. Document Revision History for Intel® MAX® 10 High-Speed LVDS I/O User Guide
1. Intel® MAX® 10 High-Speed LVDS I/O Overview x
1.1. Soft LVDS Implementation Overview
2. Intel® MAX® 10 High-Speed LVDS Architecture and Features x
2.1. Intel® MAX® 10 LVDS Channels Support 2.2. Intel® MAX® 10 LVDS SERDES I/O Standards Support 2.3. Intel® MAX® 10 High-Speed LVDS Circuitry 2.4. Intel® MAX® 10 High-Speed LVDS I/O Location 2.5. Differential I/O Pins in Low Speed Region
3. Intel® MAX® 10 LVDS Transmitter Design x
3.1. High-Speed I/O Transmitter Circuitry 3.2. LVDS Transmitter Programmable I/O Features 3.3. LVDS Transmitter I/O Termination Schemes 3.4. LVDS Transmitter FPGA Design Implementation 3.5. LVDS Transmitter Debug and Troubleshooting
3.2. LVDS Transmitter Programmable I/O Features x
3.2.1. Programmable Pre-Emphasis 3.2.2. Programmable Differential Output Voltage
3.3. LVDS Transmitter I/O Termination Schemes x
3.3.1. Emulated LVDS External Termination 3.3.2. Sub-LVDS Transmitter External Termination 3.3.3. SLVS Transmitter External Termination 3.3.4. Emulated RSDS, Emulated Mini-LVDS, and Emulated PPDS Transmitter External Termination
3.4. LVDS Transmitter FPGA Design Implementation x
3.4.1. Soft LVDS IP Core in Transmitter Mode 3.4.2. High-Speed I/O Timing Budget 3.4.3. Guidelines: LVDS Transmitter Channels Placement 3.4.4. Guidelines: LVDS Channels PLL Placement 3.4.5. Guidelines: LVDS Transmitter Logic Placement 3.4.6. Guidelines: Enable LVDS Pre-Emphasis for E144 Package
3.4.1. Soft LVDS IP Core in Transmitter Mode x
3.4.1.1. PLL Source Selection for Soft LVDS IP Core 3.4.1.2. Guidelines: LVDS TX Interface Using External PLL 3.4.1.3. Initializing the Soft LVDS IP Core
3.4.1.1. PLL Source Selection for Soft LVDS IP Core x
3.4.1.1.1. Instantiate Soft LVDS IP Core with Internal PLL 3.4.1.1.2. Instantiate Soft LVDS IP Core with External PLL
3.4.1.2. Guidelines: LVDS TX Interface Using External PLL x
3.4.1.2.1. ALTPLL Signal Interface with Soft LVDS Transmitter 3.4.1.2.24.3.1.2.2. Determining External PLL Clock Parameters for Soft LVDS Receiver3.4.1.2.24.3.1.2.2. Determining External PLL Clock Parameters for Soft LVDS Receiver
3.4.2. High-Speed I/O Timing Budget x
3.4.2.1. Transmitter Channel-to-Channel Skew
3.5. LVDS Transmitter Debug and Troubleshooting x
3.5.1. Perform RTL Simulation Before Hardware Debug 3.5.2. Geometry-Based and Physics-Based I/O Rules
4. Intel® MAX® 10 LVDS Receiver Design x
4.1. High-Speed I/O Receiver Circuitry 4.2. LVDS Receiver I/O Termination Schemes 4.3. LVDS Receiver FPGA Design Implementation 4.4. LVDS Receiver Debug and Troubleshooting
4.1. High-Speed I/O Receiver Circuitry x
4.1.1. Soft Deserializer 4.1.2. Data Realignment Block (Bit Slip)
4.2. LVDS Receiver I/O Termination Schemes x
4.2.1. LVDS, 1.8 V LVDS, Mini-LVDS, and RSDS Receiver External Termination 4.2.2. SLVS Receiver External Termination 4.2.3. Sub-LVDS Receiver External Termination 4.2.4. TMDS Receiver External Termination 4.2.5. HiSpi Receiver External Termination 4.2.6. LVPECL External Termination
4.3. LVDS Receiver FPGA Design Implementation x
4.3.1. Soft LVDS IP Core in Receiver Mode 4.3.2. High-Speed I/O Timing Budget 4.3.3. Guidelines: Floating LVDS Input Pins 4.3.4. Guidelines: LVDS Receiver Channels Placement 4.3.5. Guidelines: LVDS Channels PLL Placement 4.3.6. Guidelines: LVDS Receiver Logic Placement
4.3.1. Soft LVDS IP Core in Receiver Mode x
4.3.1.1. PLL Source Selection for Soft LVDS IP Core 4.3.1.2. Guidelines: LVDS RX Interface Using External PLL 4.3.1.3. Initializing the Soft LVDS IP Core 4.3.1.4. Guidelines: Applying Input Delay Constraint for LVDS SERDES Receiver
4.3.1.1. PLL Source Selection for Soft LVDS IP Core x
4.3.1.1.1. Instantiate Soft LVDS IP Core with Internal PLL 4.3.1.1.2. Instantiate Soft LVDS IP Core with External PLL
4.3.1.2. Guidelines: LVDS RX Interface Using External PLL x
4.3.1.2.1. ALTPLL Signal Interface with Soft LVDS Receiver 3.4.1.2.24.3.1.2.2. Determining External PLL Clock Parameters for Soft LVDS Receiver3.4.1.2.24.3.1.2.2. Determining External PLL Clock Parameters for Soft LVDS Receiver
4.3.2. High-Speed I/O Timing Budget x
4.3.2.1. Receiver Input Skew Margin 4.3.2.2. Guidelines: LVDS Receiver Timing Constraints
4.3.2.1. Receiver Input Skew Margin x
4.3.2.1.1. RSKM Equation 4.3.2.1.2. Example: RSKM Calculation
4.4. LVDS Receiver Debug and Troubleshooting x
4.4.1. Perform RTL Simulation Before Hardware Debug 4.4.2. Geometry-Based and Physics-Based I/O Rules
5. Intel® MAX® 10 LVDS Transmitter and Receiver Design x
5.1. Transmitter–Receiver Interfacing 5.2. LVDS Transmitter and Receiver FPGA Design Implementation 5.3. LVDS Transmitter and Receiver Debug and Troubleshooting
5.2. LVDS Transmitter and Receiver FPGA Design Implementation x
5.2.1. LVDS Transmitter and Receiver PLL Sharing Implementation 5.2.2. Initializing the Soft LVDS IP Core
5.3. LVDS Transmitter and Receiver Debug and Troubleshooting x
5.3.1. Perform RTL Simulation Before Hardware Debug 5.3.2. Geometry-Based and Physics-Based I/O Rules
6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations x
6.1. Guidelines: Improve Signal Quality 6.2. Guidelines: Control Channel-to-Channel Skew 6.3. Guidelines: Determine Board Design Constraints 6.4. Guidelines: Perform Board Level Simulations
7. Soft LVDS Intel® FPGA IP Core References x
7.1. Soft LVDS Intel® FPGA IP Parameter Settings 7.2. Soft LVDS Intel® FPGA IP Interface Signals
1. Intel® MAX® 10 High-Speed LVDS I/O Overview
2. Intel® MAX® 10 High-Speed LVDS Architecture and Features
3. Intel® MAX® 10 LVDS Transmitter Design
4. Intel® MAX® 10 LVDS Receiver Design
5. Intel® MAX® 10 LVDS Transmitter and Receiver Design
6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations
7. Soft LVDS Intel® FPGA IP Core References
8. Intel® MAX® 10 High-Speed LVDS I/O User Guide Archives
9. Document Revision History for Intel® MAX® 10 High-Speed LVDS I/O User Guide

7.1. Soft LVDS Intel® FPGA IP Parameter Settings

There are four groups of options: General , PLL Settings , Receiver Settings , and Transmitter Settings
Table 11.   Soft LVDS Intel® FPGA IP Parameters - General
Parameter Condition Allowed Values Description
Power Supply Mode —
  • Dual Supply
  • Single Supply
 Specifies whether the target device is a single or dual supply device.
Functional mode —
  • RX
  • TX
Specifies the functional mode for the Soft LVDS IP core:
  • RX—specifies the IP is an LVDS receiver.
  • TX—specifies the IP is an LVDS transmitter.
Number of channels — 1–18

Specifies the number of LVDS channels.

SERDES factor — 1, 2, 4, 5, 6, 7, 8, 9, 10

Specifies the number of bits per channel.
Table 12.   Soft LVDS Intel® FPGA IP Parameters - PLL Settings
Parameter Condition Allowed Values Description
Use external PLL Not applicable for x1 and x2 modes.
  • On
  • Off

Specifies whether the Soft LVDS IP core generates a PLL or connects to a user-specified PLL.

Data rate — Refer to the device datasheet.

Specifies the data rate going out of the PLL. The multiplication value for the PLL is OUTPUT_DATA_RATE divided by INCLOCK_ PERIOD.

Inclock frequency — Depends on Data rate.

Specifies the input clock frequency to the PLL in MHz.
Enable rx_locked port
  • General, Functional mode = RX
  • Use external PLL = Off
  • On
  • Off

If turned on, enables the rx_locked port.

Enable tx_locked port
  • General, Functional mode = TX
  • Use external PLL = Off
  • On
  • Off

If turned on, enables the tx_locked port.

Enable pll_areset port Use external PLL = Off
  • On
  • Off

If turned on, enables the pll_areset port in internal PLL mode.

In external PLL mode, the pll_areset port is not available.

Enable tx_data_reset port
  • General, Functional mode = TX
  • Use external PLL = On
  • On
  • Off

If turned on, enables the tx_data_reset port.

Enable rx_data_reset port
  • General, Functional mode = RX
  • Use external PLL = On
  • On
  • Off

If turned on, enables the rx_data_reset port.

Use common PLL(s) for receivers and transmitters Use external PLL = Off
  • On
  • Off
  • On—specifies that the compiler uses the same PLL for the LVDS receiver and transmitter.
  • Off—specifies that the compiler uses different PLLs for LVDS receivers and transmitters.

You can use common PLLs if you use the same input clock source, deserialization factor, pll_areset source, and data rates.

Enable self-reset on loss lock in PLL Use external PLL = Off
  • On
  • Off

If turned on, the PLL is reset when it loses lock.

Desired transmitter inclock phase shift
  • General, Functional mode = TX
  • Use external PLL = Off
Depends on Data rate.

Specifies the phase shift parameter used by the PLL for the transmitter.
Desired receiver inclock phase shift
  • General, Functional mode = RX
  • Use external PLL = Off
Depends on Data rate.

Specifies the phase shift parameter used by the PLL for the receiver.
Table 13.   Soft LVDS Intel® FPGA IP Parameters - Receiver Settings
Parameter Condition Allowed Values Description
Enable bitslip mode General, Functional mode = RX
  • On
  • Off

If turned on, enables the rx_data_align port.

Enable independent bitslip controls for each channel General, Functional mode = RX
  • On
  • Off

If turned on, enables the rx_channel_data_align port.

The rx_channel_data_align is an edge-sensitive bit slip control signal:

  • Each rising edge on this signal causes the data realignment circuitry to shift the word boundary by one bit.
  • The minimum pulse width requirement is one parallel clock cycle.
Enable rx_data_align_reset port
  • General, Functional mode = RX
  • Enable bitslip mode = On
  • Enable independent bitslip controls for each channel = Off
  • On
  • Off

If turned on, enables the rx_data_align_reset port.

Add extra register for rx_data_align port
  • General, Functional mode = RX
  • Enable bitslip mode = On
  • On
  • Off

If turned on, registers the rx_data_align port.

If you turn this option off, you must pre-register the rx_data_align[] port in the logic that feeds the receiver.

Bitslip rollover value
  • General, Functional mode = RX
  • Enable bitslip mode = On
 1–11

Specifies the number of pulses before the circuitry restores the serial data latency to 0.

Use RAM buffer —
  • On
  • Off

If turned on, the Soft LVDS IP core implements the output synchronization buffer in the embedded memory blocks.

This implementation option uses more logic than Use a multiplexer and synchronization register option but results in the correct word alignment.

Use a multiplexer and synchronization register —
  • On
  • Off

If turned on, the Soft LVDS IP core implements a multiplexer instead of a buffer for output synchronization.

Use logic element based RAM —
  • On
  • Off

If turned on, the Soft LVDS IP core implements the output synchronization buffer in the logic elements.

This implementation option uses more logic than Use a multiplexer and synchronization register option but results in the correct word alignment.

Register outputs General, Functional mode = RX
  • On
  • Off

If turned on, registers the rx_out[] port.

If you turn this option off, you must pre-register the rx_out[] port in the logic that feeds the receiver.

Table 14.   Soft LVDS Intel® FPGA IP Parameters - Transmitter Settings
Parameter Condition Allowed Values Description
Enable 'tx_outclock' output port
  • General, Functional mode = TX
  • PLL Settings, Use external PLL = Off
  • On
  • Off

If turned on, enables the tx_outclock port.

Every tx_outclock signal goes through the shift register logic, except in the following parameter configurations:

  • When the outclock_divide_by signal = 1
  • When the outclock_divide_by signal is equal to the deserialization_factor signal (for odd factors only), and the outclock_duty_cycle signal is 50
Tx_outclock division factor
  • General, Functional mode = TX
  • PLL Settings, Use external PLL = Off
  • Enable 'tx_outclock' output port = On
 Depends on SERDES factor.

Specifies that the frequency of the tx_outclock signal is equal to the transmitter output data rate divided by the selected division factor.

Outclock duty cycle
  • General, Functional mode = TX
  • PLL Settings, Use external PLL = Off
  • Enable 'tx_outclock' output port = On
 Depends on SERDES factor and Tx_outclock division factor.

Specifies the external clock timing constraints.
Desired transmitter outclock phase shift
  • General, Functional mode = TX
  • PLL Settings, Use external PLL = Off
  • Enable 'tx_outclock' output port = On
 Depends on Data rate.

Specifies the phase shift of the output clock relative to the input clock.
Register 'tx_in' input port General, Functional mode = TX
  • On
  • Off

If turned on, registers the tx_in[] port.

If you turn this option off, you must pre-register the tx_in[] port in the logic that feeds the transmitter.

Clock resource
  • General, Functional mode = TX
  • Register 'tx_in' input port = On
  • tx_inclock
  • tx_coreclock

Specifies which clock resource registers the tx_in input port.

Enable 'tx_coreclock' output port General, Functional mode = TX
  • On
  • Off

If turned on, enables the tx_coreclock output port.

Clock source for 'tx_coreclock'
  • General, Functional mode = TX
  • Enable 'tx_coreclock' output port = On
  • Auto selection
  • Global clock
  • Regional clock
  • Dual-Regional clock

Specifies which clock resource drives the tx_coreclock output port.

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