Intel® MAX® 10 High-Speed LVDS I/O User Guide

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ID 683760
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 High-Speed LVDS I/O Overview 2. Intel® MAX® 10 High-Speed LVDS Architecture and Features 3. Intel® MAX® 10 LVDS Transmitter Design 4. Intel® MAX® 10 LVDS Receiver Design 5. Intel® MAX® 10 LVDS Transmitter and Receiver Design 6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations 7. Soft LVDS Intel® FPGA IP Core References 8. Intel® MAX® 10 High-Speed LVDS I/O User Guide Archives 9. Document Revision History for Intel® MAX® 10 High-Speed LVDS I/O User Guide
1. Intel® MAX® 10 High-Speed LVDS I/O Overview x
1.1. Soft LVDS Implementation Overview
2. Intel® MAX® 10 High-Speed LVDS Architecture and Features x
2.1. Intel® MAX® 10 LVDS Channels Support 2.2. Intel® MAX® 10 LVDS SERDES I/O Standards Support 2.3. Intel® MAX® 10 High-Speed LVDS Circuitry 2.4. Intel® MAX® 10 High-Speed LVDS I/O Location 2.5. Differential I/O Pins in Low Speed Region
3. Intel® MAX® 10 LVDS Transmitter Design x
3.1. High-Speed I/O Transmitter Circuitry 3.2. LVDS Transmitter Programmable I/O Features 3.3. LVDS Transmitter I/O Termination Schemes 3.4. LVDS Transmitter FPGA Design Implementation 3.5. LVDS Transmitter Debug and Troubleshooting
3.2. LVDS Transmitter Programmable I/O Features x
3.2.1. Programmable Pre-Emphasis 3.2.2. Programmable Differential Output Voltage
3.3. LVDS Transmitter I/O Termination Schemes x
3.3.1. Emulated LVDS External Termination 3.3.2. Sub-LVDS Transmitter External Termination 3.3.3. SLVS Transmitter External Termination 3.3.4. Emulated RSDS, Emulated Mini-LVDS, and Emulated PPDS Transmitter External Termination
3.4. LVDS Transmitter FPGA Design Implementation x
3.4.1. Soft LVDS IP Core in Transmitter Mode 3.4.2. High-Speed I/O Timing Budget 3.4.3. Guidelines: LVDS Transmitter Channels Placement 3.4.4. Guidelines: LVDS Channels PLL Placement 3.4.5. Guidelines: LVDS Transmitter Logic Placement 3.4.6. Guidelines: Enable LVDS Pre-Emphasis for E144 Package
3.4.1. Soft LVDS IP Core in Transmitter Mode x
3.4.1.1. PLL Source Selection for Soft LVDS IP Core 3.4.1.2. Guidelines: LVDS TX Interface Using External PLL 3.4.1.3. Initializing the Soft LVDS IP Core
3.4.1.1. PLL Source Selection for Soft LVDS IP Core x
3.4.1.1.1. Instantiate Soft LVDS IP Core with Internal PLL 3.4.1.1.2. Instantiate Soft LVDS IP Core with External PLL
3.4.1.2. Guidelines: LVDS TX Interface Using External PLL x
3.4.1.2.1. ALTPLL Signal Interface with Soft LVDS Transmitter 3.4.1.2.24.3.1.2.2. Determining External PLL Clock Parameters for Soft LVDS Receiver3.4.1.2.24.3.1.2.2. Determining External PLL Clock Parameters for Soft LVDS Receiver
3.4.2. High-Speed I/O Timing Budget x
3.4.2.1. Transmitter Channel-to-Channel Skew
3.5. LVDS Transmitter Debug and Troubleshooting x
3.5.1. Perform RTL Simulation Before Hardware Debug 3.5.2. Geometry-Based and Physics-Based I/O Rules
4. Intel® MAX® 10 LVDS Receiver Design x
4.1. High-Speed I/O Receiver Circuitry 4.2. LVDS Receiver I/O Termination Schemes 4.3. LVDS Receiver FPGA Design Implementation 4.4. LVDS Receiver Debug and Troubleshooting
4.1. High-Speed I/O Receiver Circuitry x
4.1.1. Soft Deserializer 4.1.2. Data Realignment Block (Bit Slip)
4.2. LVDS Receiver I/O Termination Schemes x
4.2.1. LVDS, 1.8 V LVDS, Mini-LVDS, and RSDS Receiver External Termination 4.2.2. SLVS Receiver External Termination 4.2.3. Sub-LVDS Receiver External Termination 4.2.4. TMDS Receiver External Termination 4.2.5. HiSpi Receiver External Termination 4.2.6. LVPECL External Termination
4.3. LVDS Receiver FPGA Design Implementation x
4.3.1. Soft LVDS IP Core in Receiver Mode 4.3.2. High-Speed I/O Timing Budget 4.3.3. Guidelines: Floating LVDS Input Pins 4.3.4. Guidelines: LVDS Receiver Channels Placement 4.3.5. Guidelines: LVDS Channels PLL Placement 4.3.6. Guidelines: LVDS Receiver Logic Placement
4.3.1. Soft LVDS IP Core in Receiver Mode x
4.3.1.1. PLL Source Selection for Soft LVDS IP Core 4.3.1.2. Guidelines: LVDS RX Interface Using External PLL 4.3.1.3. Initializing the Soft LVDS IP Core 4.3.1.4. Guidelines: Applying Input Delay Constraint for LVDS SERDES Receiver
4.3.1.1. PLL Source Selection for Soft LVDS IP Core x
4.3.1.1.1. Instantiate Soft LVDS IP Core with Internal PLL 4.3.1.1.2. Instantiate Soft LVDS IP Core with External PLL
4.3.1.2. Guidelines: LVDS RX Interface Using External PLL x
4.3.1.2.1. ALTPLL Signal Interface with Soft LVDS Receiver 3.4.1.2.24.3.1.2.2. Determining External PLL Clock Parameters for Soft LVDS Receiver3.4.1.2.24.3.1.2.2. Determining External PLL Clock Parameters for Soft LVDS Receiver
4.3.2. High-Speed I/O Timing Budget x
4.3.2.1. Receiver Input Skew Margin 4.3.2.2. Guidelines: LVDS Receiver Timing Constraints
4.3.2.1. Receiver Input Skew Margin x
4.3.2.1.1. RSKM Equation 4.3.2.1.2. Example: RSKM Calculation
4.4. LVDS Receiver Debug and Troubleshooting x
4.4.1. Perform RTL Simulation Before Hardware Debug 4.4.2. Geometry-Based and Physics-Based I/O Rules
5. Intel® MAX® 10 LVDS Transmitter and Receiver Design x
5.1. Transmitter–Receiver Interfacing 5.2. LVDS Transmitter and Receiver FPGA Design Implementation 5.3. LVDS Transmitter and Receiver Debug and Troubleshooting
5.2. LVDS Transmitter and Receiver FPGA Design Implementation x
5.2.1. LVDS Transmitter and Receiver PLL Sharing Implementation 5.2.2. Initializing the Soft LVDS IP Core
5.3. LVDS Transmitter and Receiver Debug and Troubleshooting x
5.3.1. Perform RTL Simulation Before Hardware Debug 5.3.2. Geometry-Based and Physics-Based I/O Rules
6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations x
6.1. Guidelines: Improve Signal Quality 6.2. Guidelines: Control Channel-to-Channel Skew 6.3. Guidelines: Determine Board Design Constraints 6.4. Guidelines: Perform Board Level Simulations
7. Soft LVDS Intel® FPGA IP Core References x
7.1. Soft LVDS Intel® FPGA IP Parameter Settings 7.2. Soft LVDS Intel® FPGA IP Interface Signals
1. Intel® MAX® 10 High-Speed LVDS I/O Overview
2. Intel® MAX® 10 High-Speed LVDS Architecture and Features
3. Intel® MAX® 10 LVDS Transmitter Design
4. Intel® MAX® 10 LVDS Receiver Design
5. Intel® MAX® 10 LVDS Transmitter and Receiver Design
6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations
7. Soft LVDS Intel® FPGA IP Core References
8. Intel® MAX® 10 High-Speed LVDS I/O User Guide Archives
9. Document Revision History for Intel® MAX® 10 High-Speed LVDS I/O User Guide

2.1. Intel® MAX® 10 LVDS Channels Support

The LVDS channels available vary among Intel® MAX® 10 devices. All I/O banks in Intel® MAX® 10 support true LVDS input buffers and emulated LVDS output buffers. However, only the bottom I/O banks support true LVDS output buffers.
Note: The 1.8 V LVDS buffers are supported as inputs on all high-speed I/O banks but as outputs only on the bottom banks. The low-speed and high-speed DDR3 I/O banks do not support 1.8 V LVDS. The 1.8 V LVDS I/O standard is supported in industrial- and commercial-grade Intel® MAX® 10 dual supply devices except in packages V36 and V81. Refer to the related information.
Table 2.   LVDS Buffers in Intel® MAX® 10 Devices This table lists the LVDS buffer support for I/O banks on each side of the devices.
Product Line Package Device Power Supply Side True LVDS Pairs 1 Emulated LVDS Pairs 2
TX RX
10M02 V36 Dual Top 0 1 1
Right 0 3 3
Left 0 3 3
Bottom 3 3 3
M153 Single Top 0 12 12
Right 0 12 12
Left 0 12 12
Bottom 9 13 13
U169 Single Top 0 12 12
Right 0 17 17
Left 0 15 15
Bottom 9 14 14
U324 Single Top 0 27 27
Right 0 31 31
Left 0 28 28
Bottom 15 28 28
Dual Top 0 13 13
Right 0 24 24
Left 0 20 20
Bottom 9 16 16
E144 Single Top 0 10 10
Right 0 12 12
Left 0 11 11
Bottom 7 12 12
10M04 M153 Single Top 0 12 12
Right 0 12 12
Left 0 12 12
Bottom 9 13 13
U169 Single Top 0 12 12
Right 0 17 17
Left 0 15 15
Bottom 9 14 14
U324 Single Top 0 27 27
Right 0 31 31
Left 0 28 28
Bottom 15 28 28
Dual Top 0 27 27
Right 0 31 31
Left 0 28 28
Bottom 15 28 28
F256 Dual Top 0 19 19
Right 0 22 22
Left 0 19 19
Bottom 13 20 20
E144 Single Top 0 8 8
Right 0 12 12
Left 0 11 11
Bottom 10 10 10
10M08 V81 Single Top 0 5 5
Right 0 7 7
Left 0 6 6
Bottom 7 7 7
Dual Top 0 5 5
Right 0 7 7
Left 0 6 6
Bottom 7 7 7
M153 Single Top 0 12 12
Right 0 12 12
Left 0 12 12
Bottom 9 13 13
U169 Single Top 0 12 12
Right 0 17 17
Left 0 15 15
Bottom 9 14 14
U324 Single Top 0 27 27
Right 0 31 31
Left 0 28 28
Bottom 15 28 28
Dual Top 0 27 27
Right 0 31 31
Left 0 28 28
Bottom 15 28 28
F256 Dual Top 0 19 19
Right 0 22 22
Left 0 19 19
Bottom 13 20 20
E144 Single Top 0 8 8
Right 0 12 12
Left 0 11 11
Bottom 10 10 10
F484 Dual Top 0 27 27
Right 0 33 33
Left 0 28 28
Bottom 15 28 28
10M16 U169 Single Top 0 12 12
Right 0 17 17
Left 0 15 15
Bottom 9 14 14
U324 Single Top 0 27 27
Right 0 31 31
Left 0 28 28
Bottom 15 28 28
Dual Top 0 27 27
Right 0 31 3 31
Left 0 28 28
Bottom 15 28 28
F256 Dual Top 0 19 19
Right 0 22 3 22
Left 0 19 19
Bottom 13 20 20
E144 Single Top 0 8 8
Right 0 12 12
Left 0 11 11
Bottom 10 10 10
F484 Dual Top 0 39 39
Right 0 38 3 38
Left 0 32 32
Bottom 22 42 42
Y180 Single Top 0 14 14
Right 0 13 13
Left 0 13 13
Bottom 10 13 13
10M25 F256 Dual Top 0 19 19
Right 0 22 3 22
Left 0 19 19
Bottom 13 20 20
E144 Single Top 0 8 8
Right 0 12 12
Left 0 11 11
Bottom 10 10 10
F484 Dual Top 0 41 41
Right 0 48 3 48
Left 0 36 36
Bottom 24 46 46
10M40 F256 Dual Top 0 19 19
Right 0 22 3 22
Left 0 19 19
Bottom 13 20 20
E144 Single Top 0 9 9
Right 0 12 12
Left 0 11 11
Bottom 10 10 10
F484 Dual Top 0 41 41
Right 0 48 3 48
Left 0 36 36
Bottom 24 46 46
F672 Dual Top 0 53 53
Right 0 70 3 70
Left 0 60 60
Bottom 30 58 58
10M50 F256 Dual Top 0 19 19
Right 0 22 3 22
Left 0 19 19
Bottom 13 20 20
E144 Single Top 0 9 9
Right 0 12 12
Left 0 11 11
Bottom 10 10 10
F484 Dual Top 0 41 41
Right 0 48 3 48
Left 0 36 36
Bottom 24 46 46
F672 Dual Top 0 53 53
Right 0 70 3 70
Left 0 60 60
Bottom 30 58 58
Related Information
1 True LVDS pairs support 2.5 V and 1.8 V LVDS I/O standards.
2 Emulated LVDS pairs support only the 2.5 V LVDS I/O standard.
3 High-speed DDR3 I/O bank; supports only 2.5 V LVDS.
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