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1. Intel® MAX® 10 High-Speed LVDS I/O Overview
2. Intel® MAX® 10 High-Speed LVDS Architecture and Features
3. Intel® MAX® 10 LVDS Transmitter Design
4. Intel® MAX® 10 LVDS Receiver Design
5. Intel® MAX® 10 LVDS Transmitter and Receiver Design
6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations
7. Soft LVDS Intel® FPGA IP Core References
8. Intel® MAX® 10 High-Speed LVDS I/O User Guide Archives
9. Document Revision History for Intel® MAX® 10 High-Speed LVDS I/O User Guide
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3.3.1. Emulated LVDS External Termination
The emulated LVDS transmitter requires a three-resistor external termination scheme.
Figure 9. External Termination for Emulated LVDS TransmitterIn this figure, RS = 120 Ω and RP = 170 Ω.