Intel® Cyclone® 10 GX Native Fixed Point DSP IP Core User Guide

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ID 683739
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Cyclone® 10 GX Native Fixed Point DSP IP Core User Guide 2. Getting Started 3. Functional Description A. Document Revision History for the Cyclone® 10 GX Native Fixed Point DSP IP Core User Guide
1. Intel® Cyclone® 10 GX Native Fixed Point DSP IP Core User Guide x
1.1. Cyclone® 10 GX Native Fixed Point DSP IP Core Features
2. Getting Started x
2.1. Cyclone® 10 GX Native Fixed Point DSP IP Core Parameter Settings
2.1. Cyclone® 10 GX Native Fixed Point DSP IP Core Parameter Settings x
2.1.1. Operation Mode Tab 2.1.2. Pre-adder Tab 2.1.3. Internal Coefficient Tab 2.1.4. Accumulator/Output Cascade Tab 2.1.5. Pipelining Tab 2.1.6. Maximum Input Data Width Per Operation Mode
3. Functional Description x
3.1. Operational Modes 3.2. Optional Modules 3.3. Clocking Scheme 3.4. Cyclone® 10 GX Native Fixed Point DSP IP Core Signals
3.1. Operational Modes x
3.1.1. The 18 × 18 Full Mode 3.1.2. The 18 × 18 Sum of 2 Mode 3.1.3. The 18 × 18 Plus 36 Mode 3.1.4. The 18 × 18 Systolic Mode 3.1.5. The 27 × 27 Mode
3.1.3. The 18 × 18 Plus 36 Mode x
3.1.3.1. Using Less Than 36-bit Operand In 18 × 18 Plus 36 Mode
3.2. Optional Modules x
3.2.1. Input Cascade 3.2.2. Pre-adder 3.2.3. Internal Coefficient 3.2.4. Accumulator and Output Cascade 3.2.5. Pipeline Register
1. Intel® Cyclone® 10 GX Native Fixed Point DSP IP Core User Guide
2. Getting Started
3. Functional Description
A. Document Revision History for the Cyclone® 10 GX Native Fixed Point DSP IP Core User Guide

3.3. Clocking Scheme

The input, pipeline, and output registers in the Cyclone® 10 GX Native Fixed Point DSP IP core supports three clock sources/enables and two asynchronous clears. All input registers use aclr[0] and all pipeline and output registers use aclr[1]. Each register type can select one of the three clock sources and clock enable signals.

When you configure the Cyclone® 10 GX Native Fixed Point DSP IP core to 18 × 18 systolic operation mode, the Intel® Quartus® Prime software will set the input systolic register and the chainin systolic register clock source to the same clock source as the output register internally.

When you enable the double accumulator feature, the Intel® Quartus® Prime software will set the double accumulator register clock source to the same clock source as the output register internally.

Table 7.  Clocking Scheme Constraints

This tabe shows the constraints you must apply for all the registers clocking scheme.

Condition Constraint
When pre-adder is enabled Clock source for ay and az input registers must be the same.

Clock source for by and bz input registers must be the same.

When pipeline registers are enabled Clock source for all pipeline registers must be the same.
When any of the input registers for dynamic control signals Clock source for input registers for sub, accumulate, loadconst, and negate must be the same.
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