Turbo Intel® FPGA IP User Guide

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ID 683734
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Turbo Intel® FPGA IP 2. Getting Started with the Turbo Intel® FPGA IP 3. Parameter Settings 4. Turbo Intel® FPGA IP Functional Description A. Turbo IP User Guide Document Archives 5. Document Revision History for Turbo Intel® FPGA IP User Guide
1. About the Turbo Intel® FPGA IP x
1.1. Turbo Intel® FPGA IP Features 1.2. Turbo Intel® FPGA IP Device Family Support 1.3. Turbo IP Performance and Resource Utilization 1.4. Turbo Code Licensing Disclaimer 1.5. Release Information
2. Getting Started with the Turbo Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the IP with the RTL Simulator 2.6. Simulating the Turbo IP with the C-Model 2.7. Simulating the Turbo IP with MATLAB
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. Turbo IP Timeout Behavior
2.3. Specifying the IP Core Parameters and Options x
2.3.1. IP Core Generation Output ( Quartus® Prime Pro Edition)
4. Turbo Intel® FPGA IP Functional Description x
4.1. Turbo Encoder 4.2. Turbo Decoder 4.3. 4.4. Turbo Throughput
4.1. Turbo Encoder x
4.1.1. Turbo Encoder Data Format 4.1.2. Turbo Encoder Latency Calculation
4.2. Turbo Decoder x
4.2.1. Turbo Decoder Data Format 4.2.2. CRC24A or CRC24B Early Termination 4.2.3. Decoder Latency Calculation 4.2.4. Error Correction Performance for the Turbo Decoder
1. About the Turbo Intel® FPGA IP
2. Getting Started with the Turbo Intel® FPGA IP
3. Parameter Settings
4. Turbo Intel® FPGA IP Functional Description
A. Turbo IP User Guide Document Archives
5. Document Revision History for Turbo Intel® FPGA IP User Guide

1.1. Turbo Intel® FPGA IP Features

The Turbo Intel® FPGA IP offers the following features:
  • General features:
    • 3GPP LTE compliant with support for block sizes from 40 to 6,144.
    • 3GPP UMTS compliant with support for block sizes from 40 to 5,114.
    • C/MATLAB bit-accurate models for performance simulation or RTL test vector generation.
  • Decoder features:
    • Run time parameters for interleaver size and number of iterations.
    • Early termination with cyclical redundancy check (CRC).
    • Compile time parameters for the number of parallel engines, input precision.
    • Uses MaxLogMAP decoding algorithm.
    • Double-buffering for reduced latency real-time applications, which allows the decoder to receive data while processing the previous data block at compile time.
    • No external memory required.
  • Encoder features:
    • Run-time selectable interleaver block sizes.
    • Compile time parameters for standard (LTE or UMTS) and parallel encoding engines (1, 4 or 8) for high throughput and low latency.
    • Code rate 1/3 only. Use external rate matching for other code rates.
    • Double-buffering allows the encoder to receive data while processing the previous data block at compile time.
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