Turbo Intel® FPGA IP User Guide

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ID 683734
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Turbo Intel® FPGA IP 2. Getting Started with the Turbo Intel® FPGA IP 3. Parameter Settings 4. Turbo Intel® FPGA IP Functional Description A. Turbo IP User Guide Document Archives 5. Document Revision History for Turbo Intel® FPGA IP User Guide
1. About the Turbo Intel® FPGA IP x
1.1. Turbo Intel® FPGA IP Features 1.2. Turbo Intel® FPGA IP Device Family Support 1.3. Turbo IP Performance and Resource Utilization 1.4. Turbo Code Licensing Disclaimer 1.5. Release Information
2. Getting Started with the Turbo Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the IP with the RTL Simulator 2.6. Simulating the Turbo IP with the C-Model 2.7. Simulating the Turbo IP with MATLAB
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. Turbo IP Timeout Behavior
2.3. Specifying the IP Core Parameters and Options x
2.3.1. IP Core Generation Output ( Quartus® Prime Pro Edition)
4. Turbo Intel® FPGA IP Functional Description x
4.1. Turbo Encoder 4.2. Turbo Decoder 4.3. 4.4. Turbo Throughput
4.1. Turbo Encoder x
4.1.1. Turbo Encoder Data Format 4.1.2. Turbo Encoder Latency Calculation
4.2. Turbo Decoder x
4.2.1. Turbo Decoder Data Format 4.2.2. CRC24A or CRC24B Early Termination 4.2.3. Decoder Latency Calculation 4.2.4. Error Correction Performance for the Turbo Decoder
1. About the Turbo Intel® FPGA IP
2. Getting Started with the Turbo Intel® FPGA IP
3. Parameter Settings
4. Turbo Intel® FPGA IP Functional Description
A. Turbo IP User Guide Document Archives
5. Document Revision History for Turbo Intel® FPGA IP User Guide

3. Parameter Settings

You can customize the Turbo IP by specifying parameters in the IP parameter editor:
Table 9.  Parameters
Parameter Range Description
Turbo Specification
Standard LTE or UMTS Select LTE or UMTS.
Codec Type Encoder, Decoder Select an encoder or decoder.
Turbo Decoder Options
Number of Processors 2, 4, 8, 16, 32
Note: The UMTS supports only 2 and 4, and LTE supports 2, 4, 8, 16, 32.

Select the number of engines (N dec) that the decoder uses. The output width (W out) varies depending on the number of engines:

  • 8 bits for 8 engines or less,
  • 16 bits for 16 engines,
  • 32 bits for 32 engines
Note: For the UMTS the output width is always 1.
Number of LLRs per input 1 or 2 The number of data LLR per input symbol (N LLR). For two LLR the input symbols are Z’2 Z2 X2 Z’1 Z1 X1
Note: This parameter is not available if you select UMTS standard.
Width of the input LLRs 5, 6, 7, 8 The number of input bits (W LLR) to the decoder. Three of the bits are integer bits and the remaining bits are fractional bits:
  • 5-bit LLRs have two fractional bits.
  • 6-bit LLRs have three fractional bits.
  • 7-bit LLRs have four fractional bits.
  • 8-bit LLRs have five fractional bits.
Turbo Encoder Options
Parallelism of Encoder 1, 4, 8 Selects the number of parallel encoding engines (N enc) for LTE turbo encoder only.

For UMTS turbo encoder the value of this parameter (N enc) is 1.

This parameter is not available in the Quartus® Prime Standard Edition software IP variations.
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