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2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. IP Catalog and Parameter Editor
2.3. Specifying the IP Core Parameters and Options
2.4. Simulating Intel® FPGA IP Cores
2.5. Simulating the IP with the RTL Simulator
2.6. Simulating the Turbo IP with the C-Model
2.7. Simulating the Turbo IP with MATLAB
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4.2.4. Error Correction Performance for the Turbo Decoder
Figure 9. BER (bit error rate) Curve of LTE turbo decoder over AWGN channels, where N dec= 8, W LLR= 6, and I= 8Block sizes (K) are 6144, 4096, 2048, 1024, 512, 256, 128, 64 respectively (from left to right).
![](/content/dam/docs/us/en/683734/24-1-22-3-3/zlr1607377420747.png)
Figure 10. BLER (block error rate) Curve of LTE turbo decoder over AWGN channels, where N dec= 8, W LLR= 6, and I= 8Block sizes (K) are 6144, 4096, 2048, 1024, 512, 256, 128, 64 respectively (from left to right).
![](/content/dam/docs/us/en/683734/24-1-22-3-3/hvl1607377562070.png)
Figure 11. BER Curve of UMTS turbo decoder over AWGN channels, where N dec= 4, W LLR= 6, and I= 8Block sizes (K) are 5144, 2048, 1024, 512, 256, 128, 64 respectively (from left to right).
Figure 12. BLER Curve of UMTS turbo decoder over AWGN channels, where N dec= 4, W LLR= 6, and I= 8Block sizes (K) are 5144, 2048, 1024, 512, 256, 128, 64 respectively (from left to right).