4.1.1. Turbo Encoder Data Format
The required input data ordering for a block of size K is: X 0, X 1, X 2, . . . . X K - 1. The output data is three bits wide.
Output Data | sink_data | ||
---|---|---|---|
Nenc = 8 | Nenc = 4 | Nenc = 1 | |
0 | X 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 | X 3 X 2 X 1 X 0 | X 0 |
1 | X 15 X 14 X 13 X 12 X 11 X 10 X 9 X 8 | X 7 X 6 X 5 X 4 | X 1 |
... | ... | ... | .. |
K - 1 | - | - | X K - 1 |
K/4-1 | - | X K-1 X K-2 X K-3 X K-4 | - |
K/8-1 | X K-1 X K-2 X K-3 X K-4 X K-5 X K-6 X K-7 X K-8 | - | - |
Output Data | source_data | ||
---|---|---|---|
2 | 1 | 0 | |
0 | Z ’0 | Z 0 | X 0 |
1 | Z ’1 | Z 1 | X 1 |
... | ... | ... | .. |
K - 1 | Z ’ K - 1 | Z K - 1 | X K - 1 |
K | X K + 1 | Z K | X K |
K + 1 | Z K + 2 | X K + 2 | Z K + 1 |
K + 2 | X ’ K + 1 | Z ’ K | X ’ K |
K + 3 | Z ’ K + 2 | X ’ K + 2 | Z ’ K + 1 |
Note: The outputs of the last four clock cycles are corresponding to 12 termination bits.
Output Data | source_data | ||
---|---|---|---|
11...8 | 7...4 | 3...0 | |
0 | Z ’3 Z ’2 Z ’1 Z’0 | Z 3 Z 2 Z 1 Z 0 | X 3 X 2 X 1 X 0 |
1 | Z ’7 Z ’6 Z ’5 Z’4 | Z 7 Z 6 Z 5 Z 4 | X7X 6 X 5 X 4 |
... | ... | ... | .. |
K / 4 - 1 | Z ’K-1 Z ’K-2 Z ’K-3 Z’K-4 | Z K-1 Z K-2 Z K-3 Z K-4 | X K-1 X K-2 X K-3 X K-4 |
K / 4 | Z ’K+2 X ’K+1 Z K+2 X K+1 | X ’K+2 Z ’K X K+2 Z K | Z ’K+1 X ’K Z K+1 X K |
Note: The outputs of the last four clock cycles are corresponding to 12 termination bits.
Output Data | source_data | ||
---|---|---|---|
23...16 | 15...8 | 7...0 | |
0 | Z ’7 Z ’6 Z ’5 Z’4 Z’3 Z’2 Z’1 Z’0 | Z 7 Z 6 Z 5 Z 4 Z 3 Z 2 Z 1 Z 0 | X 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 |
1 | Z ’15 Z ’14 Z ’13 Z’12 Z’11 Z’10 Z’9 Z’8 | Z 15 Z 14 Z 13 Z 12 Z 11 Z 10 Z 9 Z 8 | X 15 X 14 X 13 X 12 X 11 X 10 X 9 X 8 |
... | ... | ... | .. |
K / 8 - 1 | Z ’K-1 Z ’K-2 Z ’K-3 Z’K-4 Z’K-5 Z’K-6 Z’K-7 Z’K-8 | Z K-1 Z K-2 Z K-3 Z K-4 Z K-5 Z K-6 Z K-7 Z K-8 | X K-1 X K-2 X K-3 X K-4 X K-5 X K-6 X K-7 X K-8 |
K / 8 | 4'bx Z ’K+2 X ’K+1 Z K+2 X K+1 | 4'bx X ’K+2 Z ’K X K+2 Z K | 4'bx Z ’K+1 X ’K Z K+1 X K |
Note: The outputs of the last clock cycles are corresponding to 12 termination bits. where output bits 23, 22, 21, 20, 15, 14, 13, 12, 7, 6, 5, 4 in the last clock cycle are unused bits.