Turbo Intel® FPGA IP User Guide

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ID 683734
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Turbo Intel® FPGA IP 2. Getting Started with the Turbo Intel® FPGA IP 3. Parameter Settings 4. Turbo Intel® FPGA IP Functional Description A. Turbo IP User Guide Document Archives 5. Document Revision History for Turbo Intel® FPGA IP User Guide
1. About the Turbo Intel® FPGA IP x
1.1. Turbo Intel® FPGA IP Features 1.2. Turbo Intel® FPGA IP Device Family Support 1.3. Turbo IP Performance and Resource Utilization 1.4. Turbo Code Licensing Disclaimer 1.5. Release Information
2. Getting Started with the Turbo Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the IP with the RTL Simulator 2.6. Simulating the Turbo IP with the C-Model 2.7. Simulating the Turbo IP with MATLAB
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. Turbo IP Timeout Behavior
2.3. Specifying the IP Core Parameters and Options x
2.3.1. IP Core Generation Output ( Quartus® Prime Pro Edition)
4. Turbo Intel® FPGA IP Functional Description x
4.1. Turbo Encoder 4.2. Turbo Decoder 4.3. 4.4. Turbo Throughput
4.1. Turbo Encoder x
4.1.1. Turbo Encoder Data Format 4.1.2. Turbo Encoder Latency Calculation
4.2. Turbo Decoder x
4.2.1. Turbo Decoder Data Format 4.2.2. CRC24A or CRC24B Early Termination 4.2.3. Decoder Latency Calculation 4.2.4. Error Correction Performance for the Turbo Decoder
1. About the Turbo Intel® FPGA IP
2. Getting Started with the Turbo Intel® FPGA IP
3. Parameter Settings
4. Turbo Intel® FPGA IP Functional Description
A. Turbo IP User Guide Document Archives
5. Document Revision History for Turbo Intel® FPGA IP User Guide

4.2.3. Decoder Latency Calculation

The decoding delay D is the number of clock cycles the IP core consumes to decode an entire block of data. D depends on the block size, the number of iterations to perform, and the number of engines available in the decoder.

The following calculations assume no early termination for the worst case latency.

You can calculate the decoding delay D using one of the following equations:

  • D = 26 + (2 × f(K,N dec ) + 14) × 2 × I , if f(K, N dec ) <= 32
  • D = 26 + (f(K,N dec ) + 46) × 2 × I , if f(K, N dec ) >= 32:

where:

  • K is the block size
  • I is the number of decoding iterations
  • N dec is the number of engines specified in the decoder
For LTE,
  • f(K,N dec) = K/min(4, N dec), if K ≤ 128.
  • f(K,N dec) = K/min(8, N dec), if 128 < K ≤ 512.
  • f(K,N dec) = K/min(16, N dec), if 512 < K ≤ 1024.
  • f(K,N dec) = K/N dec otherwise.

For UMTS, f(K,N dec) = ceil(K/N dec)

For example:

  • D = 26 + (6144/8 + 46) × 2 × 8 = 13,050, if K = 6144, N dec = 8, I = 8.
  • D = 26 + (2 × 40/4 + 14) × 2 × 8 = 544, if K = 40, N dec = 8, I = 8.

You can calculate the decoding latency (the time the decoder takes to decode an entire block to the decoded data is ready for output) using the following equation:

L = D/f s

Where f is the system clock speed.

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