Turbo Intel® FPGA IP User Guide

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ID 683734
Date 9/30/2022
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Document Table of Contents
Document Table of Contents x
1. About the Turbo Intel® FPGA IP 2. Getting Started with the Turbo Intel® FPGA IP 3. Parameter Settings 4. Turbo Intel® FPGA IP Functional Description A. Turbo IP User Guide Document Archives 5. Document Revision History for Turbo Intel® FPGA IP User Guide
1. About the Turbo Intel® FPGA IP x
1.1. Turbo Intel® FPGA IP Features 1.2. Turbo Intel® FPGA IP Device Family Support 1.3. Turbo IP Performance and Resource Utilization 1.4. Turbo Code Licensing Disclaimer 1.5. Release Information
2. Getting Started with the Turbo Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the IP with the RTL Simulator 2.6. Simulating the Turbo IP with the C-Model 2.7. Simulating the Turbo IP with MATLAB
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. Turbo IP Timeout Behavior
2.3. Specifying the IP Core Parameters and Options x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
4. Turbo Intel® FPGA IP Functional Description x
4.1. Turbo Encoder 4.2. Turbo Decoder 4.3. 4.4. Turbo Throughput
4.1. Turbo Encoder x
4.1.1. Turbo Encoder Data Format 4.1.2. Turbo Encoder Latency Calculation
4.2. Turbo Decoder x
4.2.1. Turbo Decoder Data Format 4.2.2. CRC24A or CRC24B Early Termination 4.2.3. Decoder Latency Calculation 4.2.4. Error Correction Performance for the Turbo Decoder
1. About the Turbo Intel® FPGA IP
2. Getting Started with the Turbo Intel® FPGA IP
3. Parameter Settings
4. Turbo Intel® FPGA IP Functional Description
A. Turbo IP User Guide Document Archives
5. Document Revision History for Turbo Intel® FPGA IP User Guide

1.3. Turbo IP Performance and Resource Utilization

Table 2.  Performance and Resource UtilizationTypical expected performance for a Turbo IP Core using the Quartus Prime software with the Intel® Agilex™ (AGFB014R24B2I2V), Intel® Stratix® 10 (1SG280HU2F50E2VG and 1SG280HU2F50E2LG), and Intel® Arria® 10 (10AT115S1F45E1SG) devices.
Device Speed Grade Parameters ALM Memory M20K fMAX1 (MHz)
Codec Type Standard Input Bits Engines
Intel® Agilex™ 2 Encoder LTE - 1 531 8 500
- 4 980 10 500
-- 8- 1.4K 19 500
UMTS - 1 1.1K 9 494
Decoder LTE 6 8 13.1K 29 481
8 8 15.6K 30 474
6 16 23.8K 24 472
8 16 28.7K 44 462
UMTS 6 2 4.9K 80 354
8 2 5.6K 90 334
6 4 7.3K 92 345
8 4 8.2K 97 325
Intel® Stratix® 10 2 Encoder LTE - 1 510 8 421
- 4 996 10 421
- 8 1.4K 19 383
UMTS - 1 1.1K 9 332
Decoder LTE 6 8 12.8K 29 318
8 8 15.3K 30 326
6 16 23.4K 42 317
8 16 28.0K 44 308
UMTS 6 2 4.8K 80 251
8 2 5.5K 90 238
6 4 7.0K 92 242
8 4 8.1K 97 229
2L Encoder LTE - 1 511 8 381
- 4 968 10 377
- 8 1.4K 19 362
UMTS - 1 1.1K 9 311
Decoder LTE 6 8 12.8K 29 295
8 8 15.3K 30 289
6 16 23.4K 42 293
8 16 28.0K 44 284
UMTS 6 2 4.8K 80 234
8 2 5.5K 90 219
6 4 7.0K 92 227
8 4 8.1K 97 209
Intel® Arria® 10 1 Encoder LTE - 1 460 2 435
- 4 988 10 382
- 8 1.3K 10 380
UMTS - 1 1.0K 4 310
Decoder LTE 6 8 11.2K 29 338
8 8 13.2K 30 325
6 16 20.0K 42 321
8 16 23.8K 44 313
UMTS 6 2 4.7K 71 231
8 2 5.5K 81 215
6 4 7.4K 73 224
8 4 8.5K 78 211
1 The table shows fMAX frequency reduced by 15%. The actual average is fMAX x 1.15.
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