Turbo Intel® FPGA IP User Guide

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ID 683734
Date 9/30/2022
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Document Table of Contents
Document Table of Contents x
1. About the Turbo Intel® FPGA IP 2. Getting Started with the Turbo Intel® FPGA IP 3. Parameter Settings 4. Turbo Intel® FPGA IP Functional Description A. Turbo IP User Guide Document Archives 5. Document Revision History for Turbo Intel® FPGA IP User Guide
1. About the Turbo Intel® FPGA IP x
1.1. Turbo Intel® FPGA IP Features 1.2. Turbo Intel® FPGA IP Device Family Support 1.3. Turbo IP Performance and Resource Utilization 1.4. Turbo Code Licensing Disclaimer 1.5. Release Information
2. Getting Started with the Turbo Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the IP with the RTL Simulator 2.6. Simulating the Turbo IP with the C-Model 2.7. Simulating the Turbo IP with MATLAB
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. Turbo IP Timeout Behavior
2.3. Specifying the IP Core Parameters and Options x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
4. Turbo Intel® FPGA IP Functional Description x
4.1. Turbo Encoder 4.2. Turbo Decoder 4.3. 4.4. Turbo Throughput
4.1. Turbo Encoder x
4.1.1. Turbo Encoder Data Format 4.1.2. Turbo Encoder Latency Calculation
4.2. Turbo Decoder x
4.2.1. Turbo Decoder Data Format 4.2.2. CRC24A or CRC24B Early Termination 4.2.3. Decoder Latency Calculation 4.2.4. Error Correction Performance for the Turbo Decoder
1. About the Turbo Intel® FPGA IP
2. Getting Started with the Turbo Intel® FPGA IP
3. Parameter Settings
4. Turbo Intel® FPGA IP Functional Description
A. Turbo IP User Guide Document Archives
5. Document Revision History for Turbo Intel® FPGA IP User Guide

5. Document Revision History for Turbo Intel® FPGA IP User Guide

Table 22.  Turbo C-Model versus Turbo IP Related Parameters
Document Version Intel® Quartus® Prime Version IP Version Changes
2022.09.30 22.3 22.3.0
  • Updated simulation instructions.
  • Updated performance and resources data
  • Changed description of source_blk_size signal.
  • Updated Decoder Latency Calculation
  • Updated Turbo Throughput
  • Updated graphs in Error Correction Performance for the Turbo Decoder
  • Deleted source error and sink error signals.
  • Deleted Packet Format Errors
2021.09.30 20.4 20.4.0 Added Questa simulator.
2021.03.28 20.4 20.4.0 Added Turbo C-Model versus Turbo IP Related Parameters table
2021.03.04 20.4 20.4.0 Added extra detail to Width of the input LLRs parameter.
2020.12.14 20.4 20.4.0
  • Implemented Intel® rebranding.
  • Renamed the Turbo IP to Turbo Intel® FPGA IP.
  • Removed instances of DSP Intel® FPGA IP throughout the document.
  • Made following changes in About the Turbo Intel FPGA IP chapter:
    • Added overview about the Turbo Intel FPGA IP.
    • Updated features in Turbo Intel FPGA IP Features section.
    • Added support for Intel® Stratix® 10 and Intel® Agilex™ device family.
    • Updated resource utilization numbers in Table: Performance and Resource Utilization.
    • Updated Release Information topic.
  • Made following changes in Getting Started with the Turbo Intel FPGA IP chapter:
    • Added new topic Installing and Licensing Intel FPGA IP Cores and removed Licensing IP Cores and OpenCore Plus IP Evaluation topics.
    • Renamed and updated Generating IP Cores topic to Specifying the IP Core Parameters and Options.
    • Added following new topics:
      • Simulating the Turbo IP with the RTL Simulator
      • Simulating the Turbo IP with the C-Model
      • Simulating the Turbo IP with MATLAB
  • Added new chapter Parameter Settings.
  • Added new parameters Parallelism of Encoder and Number of LLRs per input.
  • Made following changes in Turbo Intel FPGA IP Functional Description chapter:
    • Updated description in Turbo Encoder section.
    • Updated Turbo Encoder Data Format section.
    • Added examples of latency calculation in Turbo Encoder Latency Calculation section.
    • Modified signal from source_data to source_data_s.
    • Added new signal source_blk_size in Table: Turbo Decoder Signals.
    • Updated Turbo Throughput with new examples.
  • Added new section Parameter Optimization for the Turbo Decoder.
2017.11.06 17.1 -
  • Added 16 and 32 to Number of processors parameter
  • Added Number of LLRs per input t parameter
  • Added support for Intel® Cyclone® 10 devices
  • Removed product ID and vendor ID.
2016.05.06 16.0 - Corrected features list.
2015.11.11 15.1 -
  • Corrected performance table M20K and ALM entries.
  • Updated decoder block diagram
  • Removed Arria 10 performance table entry
2015.11.01 15,1 - Initial release
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