ALTPLL (Phase-Locked Loop) IP Core User Guide

Download PDF
ID 683732
Date 6/16/2017
Public
Document Table of Contents
Document Table of Contents x
ALTPLL (Phase-Locked Loop) IP Core User Guide
ALTPLL (Phase-Locked Loop) IP Core User Guide x
ALTPLL Features Ports and Parameters Design Examples Document Revision History
ALTPLL Features x
Phase-Locked Loop Types of PLLs Operation Modes Output Clocks Advanced Features PLL Output Counter Cascading
Phase-Locked Loop x
Building Blocks of a PLL PLL Behavior
Types of PLLs x
Parameter Setting Total Number of PLL Available in Each Supported Device Family
Operation Modes x
Operation Modes Supported in Each Device Family Parameter Settings Determining the PLL Lock Range Expanding the PLL Lock Range Setting Up Stratix III and Stratix IV PLLs for LVDS Interfacing Simulating External Feedback Board Delay
Output Clocks x
Parameter Settings Parameter Settings When “Set up PLL in LVDS mode” Option is Enabled Summary of PLL Output Clocks
Advanced Features x
Advanced Control Signals (pllena, areset, pfdena) Clock Switchover Spread-Spectrum Clocking Gated Lock and Self-Reset Programmable Bandwidth Advanced PLL Parameters PLL Dynamic Reconfiguration Dynamic Phase Configuration
Advanced Control Signals (pllena, areset, pfdena) x
pllena areset pfdena Parameter Settings Summary of Advanced Control Signals
Clock Switchover x
Parameter Settings Summary of Automatic Clock Switchover Feature
Spread-Spectrum Clocking x
Parameter Settings Summary of Spread-Spectrum Clocking Feature
Gated Lock and Self-Reset x
Gated Lock Self-Reset on Loss of Lock Parameter Settings Calculating the Value of Gated Lock Counter Summary of Gated Lock Signals and Self-Reset on Loss of Lock
Programmable Bandwidth x
Parameter Settings Summary of Programmable Bandwidth Support
Advanced PLL Parameters x
Advanced Parameter Settings
PLL Dynamic Reconfiguration x
Parameter Settings Summary of Supported Device Families for PLL Dynamic Reconfiguration Feature
Dynamic Phase Configuration x
Supported Devices Parameter Settings Modifying the PLL Phase Shift Step Resolution Using Advanced Parameters
Ports and Parameters x
ALTPLL Input Ports ALTPLL Output Ports ALTPLL Bidirectional Port ALTPLL Parameters
Design Examples x
Design Files Design Example 1: Differential Clock Design Example 2: Generating Clock Signals
Design Example 1: Differential Clock x
Generating a 166-MHz Differential SSTL External Clock Implementing the ddr_clk Design Functional Results — Simulate the ddr_clk Design in the ModelSim®-Altera Software
Design Example 2: Generating Clock Signals x
Generating 133-MHz, 200-MHz, and 200-MHz Time-Shifted Clocks Implementing the shift_clk Design Simulating the shift_clk Design in the ModelSim-Altera Software
ALTPLL (Phase-Locked Loop) IP Core User Guide

ALTPLL Parameters

In the ALTPLL parameters, the c[] and e[] ports are named CLK[] and EXTCLK[], respectively. This is to differentiate them from the parameters used to describe the C and E counters of the PLL.

Replace the brackets, [], in the parameter name with an integer to get the exact parameter name. For example, the C[]_HIGH parameter can have up to 10 variations as described in the parameter description. The variations are C0_HIGH, C1_HIGH, C2_HIGH, C3_HIGH, C4_HIGH, C5_HIGH, C6_HIGH, C7_HIGH, C8_HIGH, and C9_HIGH.

A string must be contained within a pair or double quotes. For example, to specify a medium bandwidth type of PLL, BANDWIDTH_TYPE=”MEDIUM”.

An integer must not be contained within a pair or double quotes. For example, to specify a 40% duty cycle for the output clock port, c5, CLK5_DUTY_CYCLE=40.

Table 18.  ALTPLL Parameters

Parameter

Type

Description

BANDWIDTH

String

Specifies the bandwidth value of the PLL in MHz. If this parameter is not specified, the Compiler automatically determines the value of the BANDWIDTH parameter to satisfy other PLL settings.

BANDWIDTH_TYPE

String

Specifies the type of bandwidth for the BANDWIDTH parameter. Values are AUTO, LOW, MEDIUM, or HIGH. If omitted, the default value is AUTO.

For the low bandwidth option, the PLL has a better jitter rejection but slower lock time. For the high bandwidth option, the PLL has a faster lock time but tracks more jitter. The medium option is a balance between the other two options.

C[]_HIGH

Integer

Specifies the value of the high period count for the corresponding counter, C[9..0]. If omitted, default is 1. Counters C[9..5] are not available in Cyclone III devices onwards.

C[]_INITIAL

Integer

Specifies the initial value for the corresponding counter, C[9..0]. If omitted, default is 1. Counters C[9..5] are not available in Cyclone III devices onwards.

C[]_LOW

Integer

Specifies the value of the low period count for the corresponding counter, C[9..0]. If omitted, default is 1. Counters C[9..5] are not available in Cyclone III devices onwards.

C[]_MODE

String

Specifies the operation mode for the counter, C[9..0]. The values are BYPASS, ODD, or EVEN. If omitted, the default is BYPASS. Counters C[9..5] are not available in Cyclone III devices onwards.

C[]_PH

Integer

Specifies the phase tap for the counter, C[9..0]. If omitted, default is 0. Counters C[9..5] are not available in Cyclone III devices onwards.

C[]_TEST_SOURCE

Integer

Specifies the test source for the counter, C[9..0]. If omitted, default is 0. Counters C[9..5] are not available in Cyclone III devices onwards.

C[]_USE_CASC_IN

String

Specifies whether to use cascade input for the counter, C[9..1]. Values are ON or OFF. If omitted, default is OFF. Counters C[9..5] are not available in Cyclone III devices onwards.

CHARGE_PUMP_CURRENT

Integer

Specifies the value of the charge pump current in microamperes (mA).

CLK[]_COUNTER

String

Specifies the counter for the corresponding output clock port, CLK[9..0]. Values are UNUSED, C0, C1, C2, C3, C4, C5, C6, C7, C8 or C9. If omitted, the default is C0. This parameter is not available for Cyclone II and Stratix II devices. Counters CLK[9..5]_COUNTER are not available for Cyclone III devices onwards.

CLK[]_DIVIDE_BY

Integer

Specifies the integer division factor for the VCO frequency of the corresponding output clock port, CLK[9..0] port. The parameter value must be greater than 0. Specify this parameter only if the corresponding CLK[9..0] port is used; however, it is not required if a Clock Settings assignment is specified for the corresponding CLK[9..0] port. If omitted, the default is 0. Parameters CLK[9..5]_DIVIDE_BY are not available in Cyclone III devices.

CLK[]_DUTY_CYCLE

Integer

Specifies the duty cycle in percentage for the corresponding output clock port, clk[9..0]. If omitted, the default is 50. Parameters CLK[9..5]_DUTY_CYCLE are not available in Cyclone III devices.

CLK[]_MULTIPLY_BY

Integer

Specifies the integer multiplication factor for the VCO frequency for the corresponding output clock port, CLK[9..0]. The parameter value must be greater than 0. Specify this parameter only if the corresponding CLK[9..0] port is used; however, it is not required if a Clock Settings assignment is specified for the corresponding CLK[9..0] port. If omitted, the default is 0. Parameters CLK[9..5]_MULTIPLY_BY are not available in Cyclone III devices.

CLK[]_OUTPUT_FREQUENCY

Integer

Specifies the output frequency of the corresponding output clock port, CLK[9..0].This parameter is ignored if the corresponding CLK[9..0] port is not used. This parameter is unavailable if multiplication or division factors are specified. If omitted, the default is 0.

CLK[]_PHASE_SHIFT

String

Specifies the phase shift for the corresponding output clock port, CLK[9..0], in picoseconds (ps). If omitted, the default is 0. Parameters CLK[9..5]_PHASE_SHIFT are not available in Cyclone III devices.

CLK[]_TIME_DELAY

String

Specifies, in picoseconds (ps), the delay value to be applied to the corresponding output clock port, CLK[9..0]. This parameter affects only the corresponding CLK[9..0] port and is independent of the corresponding CLK[9..0]_PHASE_SHIFT parameter; therefore, both parameters can be used simultaneously. If no units are specified, default is picoseconds (ps). Legal time delay values range from -3 ns to 6 ns in increments of 0.25 ns. These values should not be used as parameters except when reprogramming the PLL using the real-time programming interface.

CLK[]_USE_EVEN_COUNTER_MODE

String

Specifies whether the clock output needs to be forced to use even counter mode for the corresponding CLK[9..0] port. Values are ON or OFF. If omitted, the default is OFF.

CLK[]_USE_EVEN_ COUNTER_VALUE

String

Specifies whether the clock output needs to be forced to use even counter values for the corresponding CLK[9..0] port. Values are ON or OFF. If omitted, the default is OFF.

COMPENSATE_CLOCK

String

Specifies the output clock port which should be compensated for.

  • If the OPERATION_MODE parameter is set to normal mode, the values are CLK[], GCLK[], LCLK[] , or LVDSCLK[]. Default is CLK0.
  • If the OPERATION_MODE parameter is set to zero-delay buffer mode, value is EXTCLK[]. Default is EXTCLK0.
  • If the OPERATION_MODE parameter is set to source-synchronous mode, the values are CLK[], LCLK[], GCLK[], or LVDSCLK[]. This clock cannot be offset with respect to the reference clock. This relationship is preserved closely even upon temperature and frequency changes.
DOWN_SPREAD

String

Specifies the down spectrum percentage. Values range from 0 through 0.5.

E[]_HIGH

Integer

Specifies the high period count for the corresponding E[3..0] counter. Values range from 1 through 512. If omitted, the default is 1.

E[]_INITIAL

Integer

Specifies the initial value for the corresponding E[3..0] counter. Values range from 1 through 512. If omitted, the default is 1.

E[]_LOW

Integer

Specifies the low period count for the corresponding E[3..0] counter. Values range from 1 through 512. If omitted, the default is 1.

E[]_MODE

String

Specifies the mode for the corresponding E[3..0] counter. Values are BYPASS, ODD, or EVEN. If omitted, the default is BYPASS.

E[]_PH

Integer

Specifies the phase tap for the corresponding E[3..0] counter. Values range from 0 through 7. If omitted, the default is 0.

E[]_TIME_DELAY

String

Specifies, in nanoseconds (ns), the time delay for the corresponding E[3..0] counter. Values range from 0 ns to 3 ns. If omitted, the default is 0.

ENABLE[]_COUNTER

String

Specifies the counter for the corresponding ENABLE[1..0] port. Values are L0 or L1.

ENABLE_SWITCH_OVER_COUNTER

String

Specifies whether to use the switchover counter. Values are ON or OFF. If omitted, the value is OFF.

EXTCLK[]_COUNTER

String

Specifies the external counter for the corresponding external clock output port, EXTCLK[3..0]. Values are E0, E1, E2, or E3. If omitted, the default is E0. This parameter is only available for Stratix, Stratix GX, and Cyclone (EXTCLK0) devices.

EXTCLK[]_DIVIDE_BY

Integer

Specifies the integer division factor for the corresponding external clock output port, EXTCLK[3..0], with respect to the input clock frequency. The parameter value must be greater than 0. You can specify this parameter only if the corresponding EXTCLK[3..0] port is used; however, it is not required if a Clock Settings assignment is specified for the corresponding EXTCLK[3..0] port. If omitted, the default is 1. This parameter is not available for Stratix II devices.

EXTCLK[]_DUTY_CYCLE

Integer

Specifies the duty cycle in percentage for the corresponding external clock output port, EXTCLK[3..0]. If omitted, the default is 50. This parameter is not available for Stratix II devices.

EXTCLK[]_MULTIPLY_BY

Integer

Specifies the integer multiplication factor for the corresponding external clock output port, EXTCLK[3..0], with respect to the input clock frequency. The parameter value must be greater than 0. You can specify this parameter only if you use the corresponding EXTCLK[3..0] port. However, it is not required if a Clock Settings assignment is specified for the corresponding EXTCLK[3..0] port. If omitted, the default is 1. This parameter is not available for Stratix II devices.

EXTCLK[]_PHASE_SHIFT

String

Specifies the phase shift for the corresponding external clock output port, EXTCLK[3..0]. This parameter is not available for Stratix II devices.

EXTCLK[]_TIME_DELAY

String

Specifies, in picoseconds (ps), a delay value to be applied to the corresponding external clock output port, EXTCLK[3..0]. This parameter affects only the corresponding EXTCLK[3..0] port and is independent of the EXTCLK[3..0]_PHASE_SHIFT parameter; therefore you can use both parameters simultaneously. If no units are specified, picoseconds (ps) are assumed.

Legal values range from –3 ns to 6 ns in increments of 0.25 ns. Do not use these values as parameters except when reprogramming the PLL using the real-time programming interface. This parameter is not available for Stratix II devices.

FEEDBACK_SOURCE

String

Specifies which clock output has a board-level connection to the fbin port. If the OPERATION_MODE parameter is set to EXTERNAL_FEEDBACK, the FEEDBACK_SOURCE parameter is needed. Values are EXTCLK[]. If omitted, the value is EXTCLK0.

G[]_HIGH

Integer

Specifies the high period count for the corresponding G[3..0] counter. Values range from 1 to 512. If omitted, the default is 1.

G[]_INITIAL

Integer

Specifies the initial value for the corresponding G[3..0] counter. Values range from 1 to 512. If omitted, the default is 1.

G[]_LOW

Integer

Specifies the low period count for the corresponding G[3..0] counter. Values range from 1 to 512. If omitted, the default is 1.

G[]_MODE

String

Specifies the mode for the corresponding G[3..0] counter. Values are BYPASS, ODD, or EVEN. If omitted, the default is BYPASS.

G[]_PH

Integer

Specifies the phase tap for the corresponding G[3..0] counter. Values range from 0 to 7. If omitted, the default is 0.

G[]_TIME_DELAY

String

Specifies, in nanoseconds (ns), the time delay for the corresponding G[3..0] counter. Values range from 0 ns to 3 ns. If omitted, the default is 0.

GATE_LOCK_COUNTER

Integer

Specifies the value for the 20-bit counter that gates the locked output port before sending it to the locked port. This parameter is required for simulation in third-party simulators.

GATE_LOCK_SIGNAL

String

Specifies whether the locked port should be gated internally with a 20-bit programmable counter so it does not oscillate during initial power-up. Values are NO or YES. If omitted, default is NO.

INCLK[]_INPUT_FREQUENCY

Integer

Specifies the input frequency for the input clock port, inclk[1..0]. The compiler uses the frequency of the clk0 port to calculate the PLL parameters, but also analyzes and reports the phase shifts for the clk1 port.

INTENDED_DEVICE_FAMILY

String

This parameter is used for modeling and behavioral simulation purposes. The default is NONE

INVALID_LOCK_MULTIPLIER

Integer

Specifies the scaling factor, in half-clock cycles, for which the clock output ports must be out-of-lock before the locked pin goes low.

L[]_HIGH

Integer

Specifies the high period count for the corresponding L[1..0] counter. Values range from 1 to 512. If omitted, the default is 1.

L[]_INITIAL

Integer

Specifies the initial value for the corresponding L[1..0] counter. Values range from 1 to 512. If omitted, the default is 1.

L[]_LOW

Integer

Specifies the low period count for the corresponding L[1..0] counter. Values range from 1 to 512. If omitted, the default is 1.

L[]_MODE

String

Specifies the mode for the corresponding L[1..0] counter. Values are BYPASS, ODD or EVEN. If omitted, the default is BYPASS.

L[]_PH

Integer

Specifies the phase tap for the corresponding L[1..0] counter. Values range from 0 to 7. If omitted, the default is 0.

L[]_TIME_DELAY

String

Specifies, in nanoseconds (ns), the time delay for the corresponding L[1..0] counter. Values range from 0 ns to 3 ns. If omitted, the default is 0.

LOCK_HIGH

Integer

Specifies the number of half-clock cycles that the output clocks must be locked before the locked port goes high. This parameter is required for simulation in third-party simulators. Available for Stratix IV, Stratix III, Cyclone® 10 LP , Cyclone IV, and Cyclone III devices only.

LOCK_LOW

Integer

Specifies the number of half-clock cycles that the output clocks must be out-of-lock before the locked port goes low. This parameter is required for simulation in third-party simulators. Available for Stratix IV, Stratix III, Cyclone® 10 LP, Cyclone IV, and Cyclone III devices only.

LOCK_WINDOW_UI

String

Specifies the value of the LOCK_WINDOW_UI setting. If omitted, default is 0.05.

LOOP_FILTER_C

String

Specifies, in picofarads (pF), the value of the loop capacitor. Values range from 5 to 20 pF. The Compiler cannot achieve all values. If omitted, the default value is 10.

LOOP_FILTER_R

String

Specifies, in kilo ohms (K Ohm), the value of the loop resistor. Values range from 1 K to 20 K. The Compiler cannot achieve all values.

LPM_HINT

String

Allows you to specify Altera-specific parameters in VHDL Design Files (.vhd). The default is UNUSED.

LPM_TYPE

String

Identifies the library of parameterized modules (LPM) entity name in VHDL Design Files.

M

Integer

Specifies the modulus for the M counter. Provides direct access to the internal PLL parameters. If the M parameter is specified, all advanced parameters must be used. Values range from 1 to 512. If omitted, the default is 0.

M_INITIAL

Integer

Specifies the initial value for the M counter. Provides direct access to the internal PLL parameters. If the M_INITIAL parameter is specified, all advanced parameters must be used. Values range from 0 to 512. If omitted, the default is 0.

M_PH

Integer

Specifies the phase tap for the M counter. Values range from 0 to 7. If omitted, the default is 0.

M_TEST_SOURCE

Integer

Specifies the test source for the M counter. If omitted, default is 5.

M_TIME_DELAY

Integer

Specifies, in nanoseconds (ns), the time delay for the M counter. Values range from 0 ns through 3 ns. If omitted, the default is 0. This parameter is not available for Cyclone II and Stratix II devices.

M2

Integer

Specifies the spread spectrum modulus for the M counter. Provides direct access to the internal PLL parameters. If the M2 parameter is specified, all advanced parameters must be used. Values range from 1 to 512. If omitted, the value is 1.

N

Integer

Specifies the modulus for the N counter. Provides direct access to the internal PLL parameters. If the N parameter is specified, all advanced parameters must be used. Values range from 1 to 512. If omitted, the default is 1.

N_TIME_DELAY

Integer

Specifies, in nanoseconds (ns), the time delay for the N counter. Values range from 0 ns through 3 ns. If omitted, the default is 0. This parameter is not available for Cyclone II and Stratix II devices.

N2

Integer

Specifies the spread spectrum modulus for the N counter. Provides direct access to the internal PLL parameters. If the N2 parameter is specified, all advanced parameters must be used. Values range from 1 through 512. If omitted, the default is 1.

OPERATION_MODE

String

Specifies the operation of the PLL. Values are EXTERNAL_FEEDBACK, NO_COMPENSATION, NORMAL, ZERO_DELAY_BUFFER, and SOURCE_SYNCHRONOUS. If omitted, the default is NORMAL.

  • In no compensation mode, the PLL does not align a clock to the input, which leads to better jitter performance.
  • In source-synchronous mode, the clock delay from pin to I/O input register matches the data delay from pin to I/O input register.
  • Source-synchronous mode allows the clock delay from pin to I/O input register to match the data delay from pin to I/O input register.
  • In normal mode, the PLL compensates for the delay of the internal clock network used by the clock output specified in the COMPENSATE_CLOCK parameter. If the PLL is also used to drive an external clock output pin, a corresponding phase shift of the output pin results.
  • In zero-delay buffer mode, the PLL must feed an external clock output pin and compensate for the delay introduced by that pin. The signal observed on the pin is synchronized to the input clock. If the PLL is also used to drive the internal clock network, a corresponding phase shift of that network results.
  • In external feedback mode, the fbin input port must be connected to an input pin, and there must be a board-level connection between this input pin and an external clock output pin, which is specified with FEEDBACK_SOURCE parameter. The fbin port is aligned with the input clock. Use the maximum input delay assignment on the fbin port to specify external board delay.

Note that for source-synchronous mode and zero-delay buffer mode, you need to make assignments (in this case, the PLL_COMPENSATE assignment) in addition to setting the appropriate mode in the IP core. This allows you to specify an output pin as a compensation target for a PLL in zero-delay buffer or external feedback mode, or an input pin or a group of input pins as compensation targets for a PLL in Source- Synchronous mode.

If assigned to an output pin, the pin must be fed by the external clock output port of a PLL in a Stratix, HardCopy Stratix or Cyclone device, or the compensated clock output port of a PLL in other devices. Any other output pins fed by the same PLL generally are not delay compensated, especially if they have different I/O standards.

If assigned to an input pin or a group of input pins, the input pins must drive input registers that are clocked by the compensated clock output port of a PLL in source-synchronous mode.

This parameter is ignored if it is applied to anything other than an output or input pin as described above

PFD_MAX

Integer

Specifies the maximum value for the PFD pin. If omitted, the default is 0.

PFD_MIN

Integer

Specifies the minimum value for the PFD pin. If omitted, the default is 0.

PLL_TYPE

String

Specifies the type of PLL to instantiate. Values are AUTO, ENHANCED, FAST, TOP_BOTTOM and LEFT_RIGHT. If omitted, the default is AUTO.

PORT_ACTIVECLOCK

String

Specifies the ACTIVECLOCK port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_ARESET

String

Specifies the ARESET port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_CLK[]

String

Specifies the CLK[9..0] port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_CLKBAD[]

String

Specifies the CLKBAD[1..0] port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_CLKENA[]

String

Specifies the CLKENA[5..0] port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_CLKLOSS

String

Specifies the CLKLOSS port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_CLKSWITCH

String

Specifies the CLKSWITCH port connectivity. Values are PORT _ USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_CONFIGUPDATE

String

Specifies the CONFIGUPDATE port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_ENABLE[]

String

Specifies the ENABLE[1..0] port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_EXTCLK[]

String

Specifies the EXTCLK[3..0] port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_EXTCLKENA[]

String

Specifies the EXTCLKENA[3..0] port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_FBIN

String

Specifies the FBIN port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_FBOUT

String

Specifies the FBOUT port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_INCLK[]

String

Specifies the INCLK[1..0] port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_LOCKED

String

Specifies the LOCKED port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_PFDENA

String

Specifies the PFDENA port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_PHASECOUNTERSELECT

String

Specifies the PHASECOUNTERSELECT port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_PHASEDONE

String

Specifies the PHASEDONE port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_PHASESTEP

String

Specifies the PHASESTEP port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_PHASEUPDOWN

String

Specifies the PHASEUPDOWN port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_PLLENA

String

Specifies the PLLENA port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_SCANACLR

String

Specifies the SCANACLR port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_SCANCLK

String

Specifies the SCANCLK port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_SCANCLKENA

String

Specifies the SCANCLKENA port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_SCANDATA

String

Specifies the SCANDATA port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_SCANDONE

String

Specifies the SCANDONE port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_SCANREAD

String

Specifies the SCANREAD port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_SCANWRITE

String

Specifies the SCANWRITE port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_SCLKOUT[]

String

Specifies the SCLKOUT[1..0] port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_VCOOVERRANGE

String

Specifies the VCOOVERRANGE port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PORT_VCOUNDERRANGE

String

Specifies the VCOUNDERRANGE port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.

PRIMARY_CLOCK

String

Specifies the primary reference clock of the PLL. Values are INCLK0 or INCLK1. If omitted, the default is INCLK0. Use the clock switch scheme to switch between clocks. Automatic clock switchover is defined differently in different device families.

QUALIFY_CONF_DONE

String

The values are ON or OFF. If omitted, the default is OFF.

SCAN_CHAIN

String

Specifies the length of the scan chain. Values are LONG or SHORT. If omitted, the default is LONG. If set to LONG, the scan chain length is 10 counters. If set to SHORT, the scan chain length is 6 counters.

SCLKOUT[]_PHASE_SHIFT

String

Specifies, in picoseconds (ps), the phase shift for the corresponding sclkout[1..0] port. The maximum phase value is 7/8 of one VCO period. The VCO phase tap is shared with the corresponding clock output port, clk[1..0], and must have the same phase amount that is less than one VCO period. In LVDS mode, this parameter default value is 0.

SELF_RESET_ON_GATED_LOSS_LOCK

String

Specifies if the self-reset on gated-lock-loss feature is used. Values are ON or OFF. If omitted, the default is OFF.

SELF_RESET_ON_LOSS_LOCK

String

Specifies if the self-reset on loss lock feature is used. Values are ON or OFF. If omitted, the default is OFF.

SKIP_VCO

Integer

Specifies if the VCO is skipped. Values are ON or OFF. If omitted, the default is OFF.

SPREAD_FREQUENCY

Integer

Specifies, in picoseconds (ps), the modulation frequency for spread spectrum. If omitted, the default is 0.

SS

Integer

Specifies the modulus for the spread spectrum counter. Provides direct access to the internal PLL parameters. If the SS parameter is specified, all advanced parameters must be used. Values range from 1 to 32768. If omitted, the default is 1.

SWITCH_OVER_COUNTER

Integer

Specifies the number of clock cycles to switch the input clock after the switchover circuit is initiated. Values are 0 through 31. If omitted, the default is 0.

SWITCH_OVER_ON_GATED_LOCK

String

Specifies whether the gated-lock condition should initiate a clock switch over. Values are ON or OFF. If omitted, the value is OFF.

SWITCH_OVER_ON_LOSSCLK

String

Specifies whether the loss-of-lock condition should initiate a clock switch over. Values are ON or OFF. If omitted, the value is OFF.

SWITCH_OVER_TYPE

String

Specifies the switchover type. Values are AUTO or MANUAL. If omitted, the default is AUTO.

USING_FBMIMICBIDIR_PORT

String

Specifies whether the fbmimicbidir port is used. Values are ON or OFF. If omitted, the default is OFF.

For Stratix III and Stratix IV device families, with the OPERATION_MODE parameter set to ZERO_DELAY_BUFFER, and the USING_FBMIMICBIDIR_PORT parameter is set to OFF, you must perform the following steps:

  1. Instantiate an ALT_IOBUF IP core.
  2. Connect the fbout and fbin ports to the o and i ports of the ALT_IOBUF instantiation, respectively.
  3. Connect the bidirectional port of the ALT_IOBUF instantiation to a bidirectional pin, and set the oe port of the ALT_IOBUF instantiation to 1.

If the OPERATION_MODE parameter is set to ZERO_DELAY_BUFFER, and the USING_FBMIMICBIDIR_PORT parameter is set to ON, connect the fbmimicbidir port to a bidirectional pin. This pin must be placed on the positive feedback dedicated output pin of the PLL.

VALID_LOCK_MULTIPLIER

Integer

Specifies the scaling factor, in half-clock cycles, for which the clock output ports must be locked before the locked pin goes high.

VCO_CENTER

Integer

Specifies the center value for the VCO pin. Use for simulation purposes only.

VCO_DIVIDE_BY

Integer

Specifies the integer division factor for the VCO pin. If omitted, the default is 0. If VCO_FREQUENCY_CONTROL is set to MANUAL_PHASE, specify the VCO frequency as a phase shift step value; that is, one-eighth of the VCO period.

VCO_FREQUENCY_CONTROL

String

Specifies the integer division factor for the VCO pin. If omitted, the default is 0. If VCO_FREQUENCY_CONTROL is set to MANUAL_PHASE, specify the VCO frequency as a phase shift step value; that is, one-eighth of the VCO period.

Specifies the frequency control value for the VCO pin. Values are AUTO, MANUAL_FREQUENCY, and MANUAL_PHASE. If omitted, the default is AUTO.

  • AUTO—VCO_MULTIPLY_BY and VCO_DIVIDE_BY values are ignored and VCO frequency is set automatically.
  • MANUAL_FREQUENCY—Specifies the VCO frequency as a multiple of the input frequency.
  • MANUAL_PHASE—Specifies the VCO frequency as a phase shift step value.
VCO_MAX

Integer

Specifies the maximum value for the VCO pin. Use for simulation purposes only.

VCO_MIN

Integer

Specifies the minimum value for the VCO pin. Use for simulation purposes only.

VCO_MULTIPLY_BY

Integer

Specifies the integer multiplication factor for the VCO pin. If omitted, the default is 0.

VCO_PHASE_SHIFT_STEP

Integer

Specifies the phase shift for the VCO pin. If omitted, the default is 0.

VCO_POST_SCALE

Integer

Specifies the VCO operating range. The VCO post-scale divider value is 1 or 2. If omitted, the default is 1.

WIDTH_CLOCK

Integer

Specifies the clock width. Values are 10 for Stratix III devices, 5 for Cyclone III, Cyclone IV, and Cyclone® 10 LP devices, and 6 for all other supported device families. If omitted, the default is 6. For Stratix III, Stratix IV, Cyclone III, Cyclone IV, and Cyclone® 10 LP devices, the WIDTH_CLOCK parameter is required for both clear box and non-clear box implementation to reflect the correct width.

Related Information
Level Two Title