ALTPLL (Phase-Locked Loop) IP Core User Guide

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ID 683732
Date 6/16/2017
Public
Document Table of Contents
Document Table of Contents x
ALTPLL (Phase-Locked Loop) IP Core User Guide
ALTPLL (Phase-Locked Loop) IP Core User Guide x
ALTPLL Features Ports and Parameters Design Examples Document Revision History
ALTPLL Features x
Phase-Locked Loop Types of PLLs Operation Modes Output Clocks Advanced Features PLL Output Counter Cascading
Phase-Locked Loop x
Building Blocks of a PLL PLL Behavior
Types of PLLs x
Parameter Setting Total Number of PLL Available in Each Supported Device Family
Operation Modes x
Operation Modes Supported in Each Device Family Parameter Settings Determining the PLL Lock Range Expanding the PLL Lock Range Setting Up Stratix III and Stratix IV PLLs for LVDS Interfacing Simulating External Feedback Board Delay
Output Clocks x
Parameter Settings Parameter Settings When “Set up PLL in LVDS mode” Option is Enabled Summary of PLL Output Clocks
Advanced Features x
Advanced Control Signals (pllena, areset, pfdena) Clock Switchover Spread-Spectrum Clocking Gated Lock and Self-Reset Programmable Bandwidth Advanced PLL Parameters PLL Dynamic Reconfiguration Dynamic Phase Configuration
Advanced Control Signals (pllena, areset, pfdena) x
pllena areset pfdena Parameter Settings Summary of Advanced Control Signals
Clock Switchover x
Parameter Settings Summary of Automatic Clock Switchover Feature
Spread-Spectrum Clocking x
Parameter Settings Summary of Spread-Spectrum Clocking Feature
Gated Lock and Self-Reset x
Gated Lock Self-Reset on Loss of Lock Parameter Settings Calculating the Value of Gated Lock Counter Summary of Gated Lock Signals and Self-Reset on Loss of Lock
Programmable Bandwidth x
Parameter Settings Summary of Programmable Bandwidth Support
Advanced PLL Parameters x
Advanced Parameter Settings
PLL Dynamic Reconfiguration x
Parameter Settings Summary of Supported Device Families for PLL Dynamic Reconfiguration Feature
Dynamic Phase Configuration x
Supported Devices Parameter Settings Modifying the PLL Phase Shift Step Resolution Using Advanced Parameters
Ports and Parameters x
ALTPLL Input Ports ALTPLL Output Ports ALTPLL Bidirectional Port ALTPLL Parameters
Design Examples x
Design Files Design Example 1: Differential Clock Design Example 2: Generating Clock Signals
Design Example 1: Differential Clock x
Generating a 166-MHz Differential SSTL External Clock Implementing the ddr_clk Design Functional Results — Simulate the ddr_clk Design in the ModelSim®-Altera Software
Design Example 2: Generating Clock Signals x
Generating 133-MHz, 200-MHz, and 200-MHz Time-Shifted Clocks Implementing the shift_clk Design Simulating the shift_clk Design in the ModelSim-Altera Software
ALTPLL (Phase-Locked Loop) IP Core User Guide

ALTPLL Input Ports

Table 15.  ALTPLL Input Ports  

Port Name 6

Condition

Description

areset

Optional

Resets all counters to initial values, including the GATE_LOCK_COUNTER parameter.

c[]_ena

Optional

An enable input port for the output clock, c[]. Available for Stratix and Stratix GX devices only.

clkswitch

Optional

The control input port to dynamically toggle between clock input ports (inclk0 and inclk1 ports), or to manually override the automatic clock switchover. You should create the clkswitch port if only the inclk1 port is created.

configupdate

Optional

Dynamic full PLL reconfiguration.

e[]_ena[]

Optional

An enable input port for the external output clock, e[]. Available for Stratix and Stratix GX devices only.

fbin

Optional

The external feedback input port for the PLL.

This port must be created if the PLL operates in the external feedback mode. To complete the feedback loop, there must be a board-level connection between the fbin port and the external clock output port of the PLL.

In the Stratix III device, if the PLL operates in the zero-delay buffer mode and the fbmimicbidir port is not used, you must connect the fbin port to the fbout port.

inclk[]

Required

The clock inputs that drive the clock network.

If more than one inclk[] port is created, you must use the clkselect port to specify which clock is used. The inclk0 port must always be connected; connect other clock inputs if switching is necessary. A dedicated clock pin or PLL output clock can drive this port.

pfdena

Optional

Enables the phase frequency detector (PFD). When the PFD is disabled, the PLL continues to operate regardless of the input clock. Because the PLL output clock frequency does not change for some time, you can use the pfdena port as a shutdown or cleanup function when a reliable input clock is no longer available.

phasecounterselect[]

Optional

Specifies counter select. Only available for Arria II GX, Stratix III, and Cyclone III devices onwards.

phasestep

Optional

Specifies dynamic phase shifting. Only available for Arria II GX, Stratix III, and Cyclone III devices onwards.

phaseupdown

Optional

Specifies dynamic phase adjustment up or down. Only available for Arria II GX, Stratix III, and Cyclone III devices onwards.

pllena

Optional

The PLL enable port. When the pllena port is asserted, the PLL drives out a signal, and vice versa. When the pllena port is re-asserted, the PLL has to re-lock. All PLLs on the device share the same pllena port.

scanaclr

Optional

Asynchronous clear port for the real-time programming scan chain, or the serial scan chain. Only available for Stratix and Stratix GX devices.

scanclk

Optional

Input clock port for the serial scan chain. Not available for Cyclone and Cyclone II devices.

scanclkena

Optional

Clock enable port for the serial scan chain. Available only for Arria II GX, Cyclone III, HardCopy III, and Stratix III devices onwards.

scandata

Optional

Contains the data for the serial scan chain. Not available for Cyclone and Cyclone II devices.

scanread

Optional

Port that controls the serial scan chain to read input from the scandata port. Only available for Arria GX, HardCopy II, Stratix II, and Stratix II GX devices.

scanwrite

Optional

Port that controls the real-time programming scan chain to write to the PLL. Only available for Arria GX, HardCopy II, Stratix II, and Stratix II GX devices.

6 Replace brackets, [], in the port name with integer to get the exact name. For example, inclk0, inclk1, c1_ena, and e0_ena.
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