ALTPLL (Phase-Locked Loop) IP Core User Guide

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ID 683732
Date 6/16/2017
Public
Document Table of Contents
Document Table of Contents x
ALTPLL (Phase-Locked Loop) IP Core User Guide
ALTPLL (Phase-Locked Loop) IP Core User Guide x
ALTPLL Features Ports and Parameters Design Examples Document Revision History
ALTPLL Features x
Phase-Locked Loop Types of PLLs Operation Modes Output Clocks Advanced Features PLL Output Counter Cascading
Phase-Locked Loop x
Building Blocks of a PLL PLL Behavior
Types of PLLs x
Parameter Setting Total Number of PLL Available in Each Supported Device Family
Operation Modes x
Operation Modes Supported in Each Device Family Parameter Settings Determining the PLL Lock Range Expanding the PLL Lock Range Setting Up Stratix III and Stratix IV PLLs for LVDS Interfacing Simulating External Feedback Board Delay
Output Clocks x
Parameter Settings Parameter Settings When “Set up PLL in LVDS mode” Option is Enabled Summary of PLL Output Clocks
Advanced Features x
Advanced Control Signals (pllena, areset, pfdena) Clock Switchover Spread-Spectrum Clocking Gated Lock and Self-Reset Programmable Bandwidth Advanced PLL Parameters PLL Dynamic Reconfiguration Dynamic Phase Configuration
Advanced Control Signals (pllena, areset, pfdena) x
pllena areset pfdena Parameter Settings Summary of Advanced Control Signals
Clock Switchover x
Parameter Settings Summary of Automatic Clock Switchover Feature
Spread-Spectrum Clocking x
Parameter Settings Summary of Spread-Spectrum Clocking Feature
Gated Lock and Self-Reset x
Gated Lock Self-Reset on Loss of Lock Parameter Settings Calculating the Value of Gated Lock Counter Summary of Gated Lock Signals and Self-Reset on Loss of Lock
Programmable Bandwidth x
Parameter Settings Summary of Programmable Bandwidth Support
Advanced PLL Parameters x
Advanced Parameter Settings
PLL Dynamic Reconfiguration x
Parameter Settings Summary of Supported Device Families for PLL Dynamic Reconfiguration Feature
Dynamic Phase Configuration x
Supported Devices Parameter Settings Modifying the PLL Phase Shift Step Resolution Using Advanced Parameters
Ports and Parameters x
ALTPLL Input Ports ALTPLL Output Ports ALTPLL Bidirectional Port ALTPLL Parameters
Design Examples x
Design Files Design Example 1: Differential Clock Design Example 2: Generating Clock Signals
Design Example 1: Differential Clock x
Generating a 166-MHz Differential SSTL External Clock Implementing the ddr_clk Design Functional Results — Simulate the ddr_clk Design in the ModelSim®-Altera Software
Design Example 2: Generating Clock Signals x
Generating 133-MHz, 200-MHz, and 200-MHz Time-Shifted Clocks Implementing the shift_clk Design Simulating the shift_clk Design in the ModelSim-Altera Software
ALTPLL (Phase-Locked Loop) IP Core User Guide

ALTPLL Output Ports

Table 16.  ALTPLL Output Ports

Port Name 7

Condition

Description

activelock

Optional

Specifies which clock is used as the primary reference clock when the clock switchover circuit initiates. If the inclk0 is in use, the activeclock port goes low. If the inclk1 is in use, the activeclock port goes high.

You can set the PLL to automatically initiate the clock switchover when the primary reference clock is not toggling correctly, or you can manually initiate the clock switchover using the clkswitch input port.

c[]

Required

The clock output of the PLL.

clkbad[]

Optional

clkbad1 and clkbad0 ports check for input clock toggling. If the inclk0 port stops toggling, the clkbad0 port goes high. If the inclk1 port stops toggling, the clkbad1 port goes high.

clkloss

Optional

This output port acts as an indicator when the clock switchover circuit initiates. Only available for Arria GX, HardCopy II, Stratix, Stratix GX, Stratix II, and Stratix II GX devices.

enable[]

Optional

Enable pulse output port. This port is available only when the PLL is in LVDS mode. Only available for Arria GX, HardCopy II, Stratix II, and Stratix II GX devices.

e[]

Optional

The clock output of the PLL that feeds the dedicated clock pins on the device. Only available for Cyclone, Stratix, and Stratix GX devices.

fbout

Optional

The port that feeds the fbin port through the mimic circuitry. If a feedback path is not connected, the compiler automatically connects the fbout port directly to the fbin port. Additionally, a clkbuf primitive is added to specify the resource type used, similarly to other clock networks.

The fbout port is available only if the PLL is in external feedback mode.

For Stratix III and Stratix IV device families, if the PLL operates in zero-delay buffer mode, and the fbmimicbidir port is not used, you must perform the following steps:

  1. Replace the brackets, [], in the port name with an integer to get the exact name (for example, c0, c1, c3, e0, e1, e2, enable1 and sclkout0).
  2. Instantiate an ALT_IOBUF IP core.
  3. Connect the fbout and fbin ports to the o and i ports of the ALT_IOBUF instantiation, respectively.
  4. Connect the bidirectional port of the ALT_IOBUF instantiation to a bidirectional pin, and set the oe port of the ALT_IOBUF instantiation to 1.
locked

Optional

This output port acts as an indicator when the PLL has reached phase-locked. The locked port stays high as long as the PLL is locked, and stays low when the PLL is out-of-lock.

The number of cycles needed to gate the locked signal is based on the PLL input clock. The gated-lock circuitry is clocked by the PLL input clock. The maximum lock time for the PLL is provided in the DC and Switching Characteristics chapter of the device handbook.

Take the maximum lock time of the PLL and divide it by the period of the PLL input clock. The result is the number of clock cycles needed to gate the locked signal.

The lock signal is an asynchronous output of the PLL. The PLL lock signal is derived from the reference clock and feedback clock feeding the Phase Frequency Detector (PFD).

Reference clock = Input Clock/N Feedback clock = VCO/M

The PLL asserts the locked port when the phases and frequencies of the reference clock and feedback clock are the same or within the lock circuit tolerance. When the difference between the two clock signals goes beyond the lock circuit tolerance, the PLL loses lock.

phasedone

Optional

This output port indicates that dynamic phase reconfiguration is completed. Only available for Arria II GX, Cyclone III, HardCopy III onwards, and Stratix III onwards.

scandataout

Optional

The data output for the serial scan chain. You can use the scandataout port to determine when PLL reconfiguration is completed. The last output is cleared when reconfiguration completes. Not available for Cyclone and Cyclone II devices.

scandone

Optional

This output port indicates that the scan chain write operation is initiated. The scandone port goes high when the scan chain write operation initiates, and goes low when the scan chain write operation completes. Not available for Cyclone, Cyclone II, Stratix, and Stratix GX devices.

sclkout[]

Optional

Serial clock output port.

This port is available only when the PLL is in LVDS mode. Only available for Arria GX, HardCopy II, Stratix II, and Stratix II GX devices.

vcounverrange

Optional

This output port indicates that the VCO frequency has exceeded the legal VCO range.

vcounderrange

Optional

This output port indicates that the VCO frequency has not met the legal VCO range.

7 Replace the brackets, [], in the port name with an integer to get the exact name (for example, c0, c1, c3, e0, e1, e2, enable1 and sclkout0).
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