Intel® FPGA Download Cable II User Guide

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ID 683719
Date 8/22/2024
Public
Document Table of Contents
Document Table of Contents x
1. Setting Up the Intel® FPGA Download Cable II 2. Intel® FPGA Download Cable II Specifications 3. TCK Frequency Auto-Adjust for Intel® FPGA Download Cable II 4. Document Revision History for the Intel® FPGA Download Cable II User Guide A. Additional Information
1. Setting Up the Intel® FPGA Download Cable II x
1.1. Supported Devices and Systems 1.2. Power Source Requirements 1.3. Software Requirements and Support 1.4. Installing the Intel® FPGA Download Cable II for Configuration or Programming 1.5. Installing the Intel® FPGA Download Cable II Driver on Windows 7/8/10/11 Systems 1.6. Installing the Intel® FPGA Download Cable II Driver on Linux Systems 1.7. Setting Up the Intel® FPGA Download Cable II Hardware with the Quartus® Prime Software
2. Intel® FPGA Download Cable II Specifications x
2.1. Voltage Requirements 2.2. Cable-to-Board Connection 2.3. Intel® FPGA Download Cable II Plug Connection 2.4. 10-Pin Female Plug Signal Names and Programming Modes 2.5. Circuit Board Header Connection 2.6. Operating Conditions 2.7. JTAG Timing Constraints and Waveforms 2.8. Changing the TCK Frequency
3. TCK Frequency Auto-Adjust for Intel® FPGA Download Cable II x
3.1. Turn ON/OFF Auto-Adjust Feature
A. Additional Information x
A.1. Windows Troubleshooting Procedure for Intel® FPGA Download Cable II A.2. Troubleshooting Procedure for Error when scanning hardware - No Devices A.3. Certification Statements
A.1. Windows Troubleshooting Procedure for Intel® FPGA Download Cable II x
A.1.1. Jtagconfig Version Setting ( Quartus® Prime software root directory setting) A.1.2. Jtagserver Setting A.1.3. Install/Reinstall the Intel® FPGA Download Cable II driver
A.1.1. Jtagconfig Version Setting ( Quartus® Prime software root directory setting) x
A.1.1.1. Automatic Setting A.1.1.2. Manual Setting
A.3. Certification Statements x
A.3.1. RoHS Compliance A.3.2. USB 2.0 Certification A.3.3. CE EMI Conformity Caution
1. Setting Up the Intel® FPGA Download Cable II
2. Intel® FPGA Download Cable II Specifications
3. TCK Frequency Auto-Adjust for Intel® FPGA Download Cable II
4. Document Revision History for the Intel® FPGA Download Cable II User Guide
A. Additional Information

2.4. 10-Pin Female Plug Signal Names and Programming Modes

Table 3.  10-Pin II Female Plug Signal Names and Programming Modes
Pin Active Serial (AS) Mode Passive Serial (PS) Mode JTAG Mode
Signal Name Description 1 Signal Name Description1 Signal Name Description1
1 DCLK Configuration Clock DCLK Configuration Clock TCK Test Clock
2 GND Signal ground GND Signal ground GND Signal ground
3 CONF_DONE Configuration done CONF_DONE Configuration done TDO Test Data Output
4 VCC(TRGT) Target power supply VCC(TRGT) Target power supply VCC(TRGT) Target power supply
5 nCONFIG Configuration control nCONFIG Configuration control TMS Test Mode Select Input
6 nCE Target chip enable - - PROC_RST Processor Reset
7 DATAOUT Active serial data out nSTATUS Configuration Status - -
8 nCS Serial configuration device chip select nCS Serial configuration device chip select - -
9 ASDI Active serial data in DATA0 Passive serial data in TDI Test Data Input
10 GND Signal ground GND Signal ground GND Signal ground
Note: Use pin 6 for hard processor reset under JTAG mode.
Note: The following note below only applies to Arria® 10 and earlier SoC devices. PROC_RST is not used for Stratix® 10 and Agilex™ SoC devices.

In JTAG mode, the PROC_RST pin can be used to trigger warm reset of the HPS block when prompted via the ARM DS-5 debugger. PROC_RST is an active low signal and not an open collector pin. As such, it is not recommended to connect PROC_RST to HPS_nRST directly. You should instead connect this pin to a secondary device such as the MAX V CPLD, and use the device to manage the reset network for HPS.

1 The input or output pin described is referring to the pin of the FPGA device. For more information, refer to the Configuration User Guide or Device Pin Connection Guidelines of the respective FPGA device.
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