Intel® Cyclone® 10 GX Device Design Guidelines

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ID 683703
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 GX Device Design Guidelines
Intel® Cyclone® 10 GX Device Design Guidelines x
System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Design Entry Design Implementation, Analysis, Optimization, and Verification Design Checklist Appendix: Cyclone® 10 GX Transceiver Design Guidelines Conclusion Document Revision History
System Specification x
Design Specifications IP Selection Platform Designer
Device Selection x
Logic, Memory, and Multiplier Density I/O Pin Count, LVDS Channels, and Package Offering PLLs and Clock Routing Speed Grade Vertical Device Migration
Early System and Board Planning x
Early Power Estimation Temperature Sensing for Thermal Management Voltage Sensor Planning for Device Configuration Planning for On-Chip Debugging
Planning for Device Configuration x
Configuration Scheme Selection Configuration Features Quartus Prime Configuration Settings
Configuration Scheme Selection x
Serial Configuration Devices Download Cables Using the Parallel Flash Loader Intel® FPGA IP with MAX Devices
Configuration Features x
Data Compression Design Security Using Configuration Bitstream Encryption Remote System Upgrades SEU Mitigation and CRC Error Checks
Planning for On-Chip Debugging x
On-Chip Debugging Tools Planning Guidelines for Debugging Tools
Pin Connection Considerations for Board Design x
Device Power-Up Power Pin Connections and Power Supplies Configuration Pin Connections Board-Related Quartus Prime Settings Signal Integrity Considerations Board-Level Simulation and Advanced I/O Timing Analysis
Power Pin Connections and Power Supplies x
Decoupling Capacitors PLL and Transceiver Board Design Guidelines
Configuration Pin Connections x
DCLK and TCK Signal Integrity JTAG Pins MSEL Configuration Mode Pins Other Configuration Pins
Board-Related Quartus Prime Settings x
Device-Wide Output Enable Pin Unused Pins
Signal Integrity Considerations x
High-Speed Board Design Voltage Reference Pins Simultaneous Switching Noise I/O Termination
I/O and Clock Planning x
Making FPGA Pin Assignments Early Pin Planning and I/O Assignment Analysis I/O Features and Pin Connections Clock and PLL Selection PLL Feature Guidelines Clock Control Block I/O Simultaneous Switching Noise
I/O Features and Pin Connections x
I/O Signaling Type Selectable I/O Standards and Flexible I/O Banks Memory Interfaces Dual-Purpose and Special Pin Connections Cyclone® 10 GX I/O Features
PLL Feature Guidelines x
Clock Feedback Mode Clock Outputs
Design Entry x
Design Recommendations Using IP Cores Reconfiguration Recommended HDL Coding Styles Register Power-Up Levels and Control Signals Planning for Hierarchical and Team-Based Design
Reconfiguration x
Dynamic Reconfiguration
Planning for Hierarchical and Team-Based Design x
Planning Design Partitions Planning in Bottom-Up and Team-Based Flows Creating a Design Floorplan
Design Implementation, Analysis, Optimization, and Verification x
Selecting a Synthesis Tool Device Resource Utilization Reports Quartus Prime Messages Timing Constraints and Analysis Area and Timing Optimization Preserving Performance and Reducing Compilation Time Simulation Formal Verification Power Analysis Power Optimization
Timing Constraints and Analysis x
Recommended Timing Optimization and Analysis Assignments
Power Optimization x
Device and Design Power Optimization Techniques Quartus Prime Power Optimization Techniques
Device and Design Power Optimization Techniques x
Clock Power Management Memory Power Reduction I/O Power Guidelines
Quartus Prime Power Optimization Techniques x
Power Optimization Advisor
Appendix: Cyclone® 10 GX Transceiver Design Guidelines x
Transceiver PHY Architecture Overview Transceiver Bank Architecture PHY Layer Transceiver Components Transceiver Phase-Locked Loops Clock Generation Block (CGB) Calibration Transceiver Design Flow
PHY Layer Transceiver Components x
The GX Transceiver Channel
Transceiver Phase-Locked Loops x
Advanced Transmit (ATX) PLL Fractional PLL (fPLL) Channel PLL (CMU/CDR PLL)
Intel® Cyclone® 10 GX Device Design Guidelines

Selectable I/O Standards and Flexible I/O Banks

Cyclone® 10 GX I/O pins are arranged in groups called modular I/O banks. Depending on the device density, there are up to 6 I/O banks.
Table 39.  Selectable Standards and Flexible I/O Banks Checklist
Number Done? Checklist Item
1   Select a suitable signaling type and I/O standard for each I/O pin. The I/O banks are located in I/O columns. Each I/O bank contains its own PLL, DPA, and SERDES circuitries.
2   Ensure that the appropriate I/O standard support is supported in the targeted I/O bank.
3   Place I/O pins that share voltage levels in the same I/O bank.
4   Verify that all output signals in each I/O bank are intended to drive out at the bank’s VCCIO voltage level.
5   Verify that all voltage-referenced signals in each I/O bank are intended to use the bank’s VREF voltage level.
6   Check the I/O bank support for LVDS and transceiver features.

You can assign I/O standards and make other I/O-related settings in the Pin Planner. Be sure to use the correct dedicated pin inputs for signals such as clocks and global control signals.

For more information about, refer to “Clock and PLL Selection”.

The board must supply each bank with one VCCIO voltage level for every VCCIO pin in a bank. Each I/O bank is powered by the VCCIO pins of that particular bank, and is independent of the VCCIO pins of other I/O banks. A single I/O bank supports output signals that are driving at the same voltage as the VCCIO. An I/O bank can simultaneously support any number of input signals with different I/O standards.

To accommodate voltage-referenced I/O standards, each I/O bank supports multiple VREF pins feeding a common VREF bus. Set the VREF pins to the correct voltage for the I/O standards in the bank. Each I/O bank can only have a single VCCIO voltage level and a single VREF voltage level at a given time. If the VREF pins are not used as voltage references, they cannot be used as generic I/O pins and should be tied to VCCIO of that same bank or GND.

An I/O bank including single-ended or differential standards can support voltage-referenced standards as long as all voltage-referenced standards use the same VREF setting. Voltage-referenced bi-directional and output signals must drive out at the I/O bank’s VCCIO voltage level.

Different I/O banks include different support for LVDS signaling, and the Cyclone 10 GX transceiver banks include additional support. There are two types of I/O banks, LVDS and 3 V.

The LVDS I/O bank supports differential and single-ended I/O standards up to 1.8 V. The LVDS I/O pins form pairs of true differential LVDS channels. Each pair supports a parallel input/output termination between the two pins.

The 3 V I/O bank supports only single-ended I/O standards up to 3 V. Each adjacent I/O pair also supports Differential SSTL and Differential HSTL I/O standards. The single-ended output of the 3 V I/O has the same set of features as the single-ended output of the DDR I/O IP, except the programmable pre-emphasis feature.

Refer to the Cyclone® 10 GX I/O banks figure that shows the location of each I/O bank and what each bank supports. The figures describing the number of I/Os in each bank provide bank information specific to each device density. Refer to the section describing I/O bank restrictions for information about which I/O standards can be combined in each bank, and the section describing I/O placement guidelines for details about LVDS restrictions.

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