Intel® Cyclone® 10 GX Device Design Guidelines

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ID 683703
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 GX Device Design Guidelines
Intel® Cyclone® 10 GX Device Design Guidelines x
System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Design Entry Design Implementation, Analysis, Optimization, and Verification Design Checklist Appendix: Cyclone® 10 GX Transceiver Design Guidelines Conclusion Document Revision History
System Specification x
Design Specifications IP Selection Platform Designer
Device Selection x
Logic, Memory, and Multiplier Density I/O Pin Count, LVDS Channels, and Package Offering PLLs and Clock Routing Speed Grade Vertical Device Migration
Early System and Board Planning x
Early Power Estimation Temperature Sensing for Thermal Management Voltage Sensor Planning for Device Configuration Planning for On-Chip Debugging
Planning for Device Configuration x
Configuration Scheme Selection Configuration Features Quartus Prime Configuration Settings
Configuration Scheme Selection x
Serial Configuration Devices Download Cables Using the Parallel Flash Loader Intel® FPGA IP with MAX Devices
Configuration Features x
Data Compression Design Security Using Configuration Bitstream Encryption Remote System Upgrades SEU Mitigation and CRC Error Checks
Planning for On-Chip Debugging x
On-Chip Debugging Tools Planning Guidelines for Debugging Tools
Pin Connection Considerations for Board Design x
Device Power-Up Power Pin Connections and Power Supplies Configuration Pin Connections Board-Related Quartus Prime Settings Signal Integrity Considerations Board-Level Simulation and Advanced I/O Timing Analysis
Power Pin Connections and Power Supplies x
Decoupling Capacitors PLL and Transceiver Board Design Guidelines
Configuration Pin Connections x
DCLK and TCK Signal Integrity JTAG Pins MSEL Configuration Mode Pins Other Configuration Pins
Board-Related Quartus Prime Settings x
Device-Wide Output Enable Pin Unused Pins
Signal Integrity Considerations x
High-Speed Board Design Voltage Reference Pins Simultaneous Switching Noise I/O Termination
I/O and Clock Planning x
Making FPGA Pin Assignments Early Pin Planning and I/O Assignment Analysis I/O Features and Pin Connections Clock and PLL Selection PLL Feature Guidelines Clock Control Block I/O Simultaneous Switching Noise
I/O Features and Pin Connections x
I/O Signaling Type Selectable I/O Standards and Flexible I/O Banks Memory Interfaces Dual-Purpose and Special Pin Connections Cyclone® 10 GX I/O Features
PLL Feature Guidelines x
Clock Feedback Mode Clock Outputs
Design Entry x
Design Recommendations Using IP Cores Reconfiguration Recommended HDL Coding Styles Register Power-Up Levels and Control Signals Planning for Hierarchical and Team-Based Design
Reconfiguration x
Dynamic Reconfiguration
Planning for Hierarchical and Team-Based Design x
Planning Design Partitions Planning in Bottom-Up and Team-Based Flows Creating a Design Floorplan
Design Implementation, Analysis, Optimization, and Verification x
Selecting a Synthesis Tool Device Resource Utilization Reports Quartus Prime Messages Timing Constraints and Analysis Area and Timing Optimization Preserving Performance and Reducing Compilation Time Simulation Formal Verification Power Analysis Power Optimization
Timing Constraints and Analysis x
Recommended Timing Optimization and Analysis Assignments
Power Optimization x
Device and Design Power Optimization Techniques Quartus Prime Power Optimization Techniques
Device and Design Power Optimization Techniques x
Clock Power Management Memory Power Reduction I/O Power Guidelines
Quartus Prime Power Optimization Techniques x
Power Optimization Advisor
Appendix: Cyclone® 10 GX Transceiver Design Guidelines x
Transceiver PHY Architecture Overview Transceiver Bank Architecture PHY Layer Transceiver Components Transceiver Phase-Locked Loops Clock Generation Block (CGB) Calibration Transceiver Design Flow
PHY Layer Transceiver Components x
The GX Transceiver Channel
Transceiver Phase-Locked Loops x
Advanced Transmit (ATX) PLL Fractional PLL (fPLL) Channel PLL (CMU/CDR PLL)
Intel® Cyclone® 10 GX Device Design Guidelines

Clock and PLL Selection

Table 44.  Clock and PLL Selection Checklist
Number Done? Checklist Item
1   Use the correct dedicated clock pins and routing signals for clock and global control signals.
2   Use the device PLLs for clock management.
3   Analyze input and output routing connections for each PLL and clock pin. Ensure PLL inputs come from the dedicated clock pins or from another PLL.

The first stage in planning your clocking scheme is to determine your system clock requirements. Understand your device’s available clock resources and correspondingly plan the design clocking scheme. Consider your requirements for timing performance, and how much logic is driven by a particular clock.

Cyclone® 10 GX devices provide dedicated low-skew and high fan-out routing networks. They are organized in a hierarchical structure that provides up to 208 unique clock domains within the device (32 GCLKs + 8 RCLKs + 144 SPCLKs + 24 LPCLKs). There are six fractional PLLs per device with four independently-programmable outputs per fractional PLL, and six I/O PLLs per device with up to nine independently programmable output per I/O PLLs. You can use 16 differential clock input pins or 36 single-ended clock input pins.

The dedicated clock pins drive the clock network directly, ensuring lower skew than other I/O pins. Use the dedicated routing network to have a predictable delay with less skew for high fan-out signals. You can also use the clock pins and clock network to drive control signals like asynchronous reset.

Connect clock inputs to specific PLLs to drive specific low-skew routing networks. Analyze the global resource availability for each PLL and the PLL availability for each clock input pin.

Use the following descriptions to help determine which clock networks are appropriate for the clock signals in your design:

  • The GCLK networks can drive throughout the entire device, serving as low-skew clock sources for device logic. This clock region has the maximum delay compared to other clock regions but allows the signal to reach everywhere within the device. This option is good for routing global reset/clear signals or routing clocks throughout the device.
  • The RCLK networks only pertain to the quadrant they drive into and provide the lowest clock delay and skew for logic contained within a single device quadrant.
  • IOEs and internal logic can also drive GCLKs and RCLKs to create internally generated GCLKs or RCLKs and other high fan-out control signals; for example, synchronous or asynchronous clears and clock enables.
  • PLLs cannot be driven by internally-generated GCLKs or RCLKs. The input clock to the PLL must come from dedicated clock input pins or from another pin/PLL-fed GCLK or RCLK.
  • PCLK networks are a collection of individual clock networks driven from the periphery of the Cyclone® 10 GX device. Clock outputs from the DPA block, PLD-transceiver interface, I/O pins, and internal logic can drive the PCLK networks. These PCLKs have higher skew compared to GCLK and RCLK networks and can be used instead of general purpose routing to drive signals into and out of the Cyclone® 10 GX device.

If your system requires more clock or control signals than are available in the target device, consider cases where the dedicated clock resource could be spared, particularly low fan-out and low-frequency signals where clock delay and clock skew do not have a significant impact on the design performance. Use the Global Signal assignment in the Intel® Quartus® Prime Assignment Editor to select the type of global routing, or set the assignment to Off to specify that the signal should not use any global routing resources.

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