AN 882: Using ADI AD9217 with Intel® Stratix® 10 Devices

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ID 683700
Date 8/17/2020
Public
Document Table of Contents
Document Table of Contents x
1. Using ADI AD9217 with Intel Stratix 10 Devices
1. Using ADI AD9217 with Intel Stratix 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Design Description 1.4. Functional Description 1.5. Parameterization 1.6. Directory Structure 1.7. Simulation 1.8. Latency Measurement for 10G Design 1.9. Register Map 1.10. Document Revision History for AN 882: Using ADI AD9217 with Intel Stratix 10 Devices 1.11. Appendix: 5G Design Example
1.3. Design Description x
1.3.1. Overall Design Flow 1.3.2. Low-Latency C2C Interface
1.3.2. Low-Latency C2C Interface x
1.3.2.1. Lane Mapping in C2C 1.3.2.2. C2C Design Flow 1.3.2.3. Calibration Operation Sequence 1.3.2.4. Calibration Operation Sequence Descriptions
1.5. Parameterization x
1.5.1. Design Parameters 1.5.2. Derived Parameters 1.5.3. Clocks
1.7. Simulation x
1.7.1. Procedure
1.8. Latency Measurement for 10G Design x
1.8.1. Latency Calculations
1.11. Appendix: 5G Design Example x
1.11.1. Hardware Setup 1.11.2. Parameterization 1.11.3. Directory Structure 1.11.4. Simulation 1.11.5. Hardware Testing 1.11.6. Latency Measurement for 5G Design
1.11.2. Parameterization x
1.11.2.1. Design Parameters 1.11.2.2. Derived Parameters 1.11.2.3. Clocks
1.11.4. Simulation x
1.11.4.1. Procedure
1.11.5. Hardware Testing x
1.11.5.1. Procedure
1.11.6. Latency Measurement for 5G Design x
1.11.6.1. Latency Calculations
1. Using ADI AD9217 with Intel Stratix 10 Devices

1. Using ADI AD9217 with Intel Stratix 10 Devices

AD9217 is a single 12-bit, 10.25 gigasample per second (GSPS) radio frequency (RF) analog-to-digital converter (ADC) from Analog Devices Inc. (ADI).

AD9217 features a high speed parallel output interface to support its maximum bandwidth capability. It includes digital data path that can be configured for direct real or down converted to complex intelligence quotient (IQ) data. The interface includes 12 data lines, single data clock operating at one-half of ADC sample rate, and a parity bit.

  • Data outputs are scrambled to maintain direct current (DC) balance on each data lane. During calibration, the scrambler should remain off.
  • A parity bit is generated for each 12-bit sample to detect single bit errors that result from channel-to-channel misalignment. The parity bit is passed along simultaneously with the data sample and it is determined prior to being scrambled.
  • The data clock operates at one-half the data rate. Data and the parity bit operate up to 10 Gbps while the clock operates up to 5 GHz.

AD9217 has a low latency chip-to-chip (C2C) output data formats.

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