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1. Overview of the Early Power Estimator for Intel® Arria® 10
2. Setting Up the Early Power Estimator for Intel® Arria® 10
3. Early Power Estimator for Intel® Arria® 10 Graphical User Interface
4. Early Power Estimator Worksheets for Intel® Arria® 10
5. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Arria® 10
6. Document Revision History for Early Power Estimator for Intel Arria® 10 FPGAs User Guide
A. Measuring Static Power
4.1. Arria® 10 EPE - Common Worksheet Elements
4.2. Arria® 10 EPE - Main Worksheet
4.3. Arria® 10 EPE - Logic Worksheet
4.4. Arria® 10 EPE - RAM Worksheet
4.5. Arria® 10 EPE - DSP Worksheet
4.6. Arria® 10 EPE - Clock Worksheet
4.7. Arria® 10 EPE - PLL Worksheet
4.8. Arria® 10 EPE - I/O Worksheet
4.9. Arria® 10 EPE - I/O-IP Worksheet
4.10. Arria® 10 EPE - XCVR Worksheet
4.11. Arria® 10 EPE - HPS Worksheet
4.12. Arria® 10 EPE - Report Worksheet
4.13. Arria® 10 EPE - Enpirion Worksheet
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4.7. Arria® 10 EPE - PLL Worksheet
Each row in the PLL worksheet of the Early Power Estimator (EPE) for Arria® 10 represents one or more PLLs in the device.
For Arria® 10 devices, the supported PLL types are IOPLL, fPLL, ATX PLL, and CMU PLL.
Figure 17. PLL Worksheet of the Early Power Estimator
Column Heading | Description |
---|---|
Module | Specify a name for the PLL in this column. This is an optional value. |
PLL Type | Select whether the PLL is an IOPLL, fPLL, ATX PLL, or CMU PLL. |
# PLL Blocks | Enter the number of PLL blocks with the same combination of parameters. |
# Counters | Enter the number of counters of the PLL. For fPLL, this includes C counter, L counter, and feedback. This field is not applicable for ATX PLLs and CMU PLLs. |
VCCR_GXB and VCCT_GXB Voltage | Specify the voltage of the VCCR_GXB and VCCT_GXB rails. This field is not applicable for I/O PLLs. |
Output Freq (MHz) | Specify the output frequency for CMU and ATX PLLs. |
VCO Freq (MHz) | Specify the internal VCO operating frequency for fPLLs and I/O PLLs. When using an fPLL as a transmitter PLL for XCVR channels, the VCO frequency has to be such that the required fPLL output frequency can be achieved using a legal value of the counter used for HSSI clock output. |
Total Power (W) | Shows the total estimated power for this row (in W). |
User Comments | Enter any comments. This is an optional entry. |
For more information about the PLLs available in Arria® 10 devices, refer to the Clock Networks and PLLs chapter of the Arria® 10 Device Handbook.