Early Power Estimator for Intel® Arria® 10 FPGAs User Guide

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ID 683688
Date 9/27/2022
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Early Power Estimator for Intel® Arria® 10 2. Setting Up the Early Power Estimator for Intel® Arria® 10 3. Early Power Estimator for Intel® Arria® 10 Graphical User Interface 4. Early Power Estimator Worksheets for Intel® Arria® 10 5. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Arria® 10 6. Document Revision History for Early Power Estimator for Intel Arria® 10 FPGAs User Guide A. Measuring Static Power
1. Overview of the Early Power Estimator for Intel® Arria® 10 x
1.1. Power Model Status
2. Setting Up the Early Power Estimator for Intel® Arria® 10 x
2.1. System Requirements 2.2. Download and Install the Early Power Estimator 2.3. Estimating Power Consumption
2.2. Download and Install the Early Power Estimator x
2.2.1. Changing the Macro Security Level in Microsoft Excel* 2003 2.2.2. Changing the Macro Security Level in Microsoft Excel* 2007 2.2.3. Changing the Macro Security Level in Microsoft Excel* 2010
2.3. Estimating Power Consumption x
2.3.1. Estimating Power Consumption Before Starting the FPGA Design 2.3.2. Estimating Power Consumption While Creating the FPGA Design 2.3.3. Estimating Power Consumption After Completing the FPGA Design
3. Early Power Estimator for Intel® Arria® 10 Graphical User Interface x
3.1. Early Power Estimator Input Fields 3.2. Early Power Estimator Output Fields 3.3. Early Power Estimator Input/Output Fields 3.4. Early Power Estimator Field Shading 3.5. Early Power Estimator Input Field Dependencies 3.6. Early Power Estimator Buttons
4. Early Power Estimator Worksheets for Intel® Arria® 10 x
4.1. Arria® 10 EPE - Common Worksheet Elements 4.2. Arria® 10 EPE - Main Worksheet 4.3. Arria® 10 EPE - Logic Worksheet 4.4. Arria® 10 EPE - RAM Worksheet 4.5. Arria® 10 EPE - DSP Worksheet 4.6. Arria® 10 EPE - Clock Worksheet 4.7. Arria® 10 EPE - PLL Worksheet 4.8. Arria® 10 EPE - I/O Worksheet 4.9. Arria® 10 EPE - I/O-IP Worksheet 4.10. Arria® 10 EPE - XCVR Worksheet 4.11. Arria® 10 EPE - HPS Worksheet 4.12. Arria® 10 EPE - Report Worksheet 4.13. Arria® 10 EPE - Enpirion Worksheet
5. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Arria® 10 x
5.1. Toggle Rate 5.2. Airflow 5.3. Temperature 5.4. Heat Sink
1. Overview of the Early Power Estimator for Intel® Arria® 10
2. Setting Up the Early Power Estimator for Intel® Arria® 10
3. Early Power Estimator for Intel® Arria® 10 Graphical User Interface
4. Early Power Estimator Worksheets for Intel® Arria® 10
5. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Arria® 10
6. Document Revision History for Early Power Estimator for Intel Arria® 10 FPGAs User Guide
A. Measuring Static Power

5.2. Airflow

It is often difficult to place the device adjacent to the fan providing the airflow. The path of the airflow might traverse a length on the board before reaching the device, thus diminishing the actual airflow the device receives. The following figure shows a fan that is placed at the end of the board. The airflow at the FPGA is weaker than the airflow at the fan.

Figure 27. Airflow and FPGA Position

You must also consider blocked airflow. The following figure shows a device blocking the airflow from the FPGA, significantly reducing the airflow seen at the FPGA. The airflow from the fan also has to cool board components and other devices before reaching the FPGA.

Figure 28. Airflow with Component and FPGA Positions

If you are using a custom heat sink, you do not need to enter the airflow directly into the EPE spreadsheet but it is required to enter the θSA value for the heat sink with the knowledge of what the airflow is at the device. Most heat sinks have fins located above the heat sink to facilitate airflow. The following figure shows the FPGA with a heat sink.

Figure 29. Airflow and Heat Sinks

When placing the heat sink on the FPGA, the direction of the fins must correspond with the direction of the airflow. A top view shows the correct orientation of the fins.

Figure 30. Heat Sink (Top View)

These considerations can influence the airflow at the device. When entering information into the EPE spreadsheet, you have to consider these implications to get an accurate airflow value at the FPGA.

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