eCPRI Intel® FPGA IP User Guide

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ID 683685
Date 5/19/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. IP Parameters 4. Functional Description 5. Interface Overview 6. IP Registers 7. eCPRI Intel FPGA IP User Guide Archives 8. Document Revision History for eCPRI Intel® FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. eCPRI Intel® FPGA IP Device Speed Grade Support 1.4. Resource Utilization 1.5. Intel® FPGA IP Core Verification 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. Interfaces 4.2. High Level Data Path Flow 4.3. Operation of the eCPRI IP Blocks
4.2. High Level Data Path Flow x
4.2.1. Transmit TX Path 4.2.2. Receive RX Path 4.2.3. Supported Ethernet Variants
4.3. Operation of the eCPRI IP Blocks x
4.3.1. Packet Classifier 4.3.2. Ethernet Header Insertion/Removal 4.3.3. Concatenation/De-concatenation 4.3.4. Header Mapper/De-Mapper 4.3.5. eCPRI IWF Type 0 4.3.6. eCPRI Message 5 Packet Parser 4.3.7. Packet Queue 4.3.8. eCPRI Message Type 4.3.9. Error Handling 4.3.10. RX Throttling
4.3.8. eCPRI Message Type x
4.3.8.1. eCPRI Message Type 0- IQ Data Transfer 4.3.8.2. eCPRI Message Type 1- Bit Sequence Transfer 4.3.8.3. eCPRI Message Type 2- Real Time Control Data 4.3.8.4. eCPRI Message Type 3- Generic Data Transfer 4.3.8.5. eCPRI Message Type 4- Remote Memory Access 4.3.8.6. eCPRI Message Type 5- One-Way Delay Measurement 4.3.8.7. eCPRI Message Type 6- Remote Reset 4.3.8.8. eCPRI Message Type 7- Event Indication 4.3.8.9. eCPRI Message Type 64- 255 Vendor Specific
5. Interface Overview x
5.1. Clock Signals 5.2. Power, Reset, and Firewalls Signals 5.3. TX Time of Day Interface 5.4. RX Time of Day Interface 5.5. Interrupt 5.6. Configuration Avalon® Memory-Mapped Interface 5.7. Ethernet MAC Source Interface 5.8. Ethernet MAC Sink Interface 5.9. External ST Source Interface 5.10. External ST Sink Interface 5.11. eCPRI IP Source Interface 5.12. eCPRI IP Sink Interface 5.13. Miscellaneous Interface Signals 5.14. IWF Type 0 eCPRI Interface 5.15. IWF Type 0 CPRI MAC Interface
5.2. Power, Reset, and Firewalls Signals x
5.2.1. Reset Control and Initialization Flows
5.7. Ethernet MAC Source Interface x
5.7.1. E-tile Hard IP for Ethernet 1588 PTP Signals 5.7.2. 25G Ethernet MAC 1588 PTP Signals 5.7.3. 10G Ethernet MAC 1588 PTP Signals
5.14. IWF Type 0 eCPRI Interface x
5.14.1. IWF Source Interface 5.14.2. IWF Sink Interface
5.15. IWF Type 0 CPRI MAC Interface x
5.15.1. CPRI 32-bit IQ Data TX Interface 5.15.2. CPRI 64-bit IQ Data TX Interface 5.15.3. CPRI 32-bit Ctrl_AxC TX Interface 5.15.4. CPRI 64-bit Ctrl_AxC TX Interface 5.15.5. CPRI 32-bit Vendor Specific TX Interface 5.15.6. CPRI 64-bit Vendor Specific TX Interface 5.15.7. CPRI 32-bit Real-time Vendor Specific TX Interface 5.15.8. CPRI 64-bit Real-time Vendor Specific TX Interface 5.15.9. CPRI Gigabit Media Independent Interface (GMII) 5.15.10. CPRI IP L1 Control and Status Interface
1. Introduction
2. Getting Started
3. IP Parameters
4. Functional Description
5. Interface Overview
6. IP Registers
7. eCPRI Intel FPGA IP User Guide Archives
8. Document Revision History for eCPRI Intel® FPGA IP User Guide

4.2.1. Transmit TX Path

There are two sets of Avalon® streaming interface source and sink signals available to the incoming packets on the transmit TX path. Avalon® streaming interface source/sink connects to the eCPRI IP and external source/sink interface connects to external user logic. The incoming eCPRI packets passes through Ethernet header insertion block to insert Ethernet header, optionally with different VLAN tags, IPv4, and UDP headers configured during configuration time.

You can send different types of packets through the external source/sink interface signal (For example, C&M and synchronization packets) which arbitrates with eCPRI packets and the IP sends packets with the higher priority to Ethernet MAC for transmission. The incoming external user packets are expected to arrive with Ethernet MAC header inserted on the packets.

The eCPRI IP supports two types of packets arbitration:
  • Fixed priority arbitration
  • L2 CoS priority arbitration based on the O-RAN Control, User and Synchronization Plane Specification 7.01 (ORAN-WG4.CUS.0-v07.01), Section 5.3 Quality of Service.
Both of the arbitration features are mutually exclusive to each other and you can enable one of them using the Packets Arbitration Scheme parameter.
For fixed priority arbitration, the priority of the packets send to Ethernet MAC is listed as below, with highest priority order from top to bottom:
  • PTP synchronization packet
  • eCPRI packet
  • C&M packets and remaining type of packets

The C&M and PTP synchronization packets are send/receive through external source/sink interface signal. The C&M and PTP synchronization packets are generally low bandwidth traffic. When there is collision between external PTP synchronization packets and eCPRI packets, backpressure to the eCPRI IP occurs to stop eCPRI packets from transmitting. The eCPRI IP implements a counter to track the number of eCPRI packets and PTP packets granted and raise the priority of the C&M packet when the counter reaches a programmable threshold to allow the C&M packet transmission to Ethernet MAC and avoid starvation.

Ensure the bandwidth of external source/sink interface signal won't starve the overall bandwidth and cause interruption on eCPRI traffics. The grant ratio between C&M packets versus eCPRI/PTP packets is 10:1. The bandwidth allocated to C&M packets is 2.5G or 1G. The maximum C&M/PTP FIFO depth is 256 or 2048 bytes for eCPRI IP. The C&M/PTP FIFO should not be kept full beyond 2062.5 * (mac_clk_tx) clock period, to allow for enough read margin prior to the arrival of the new packets.

When you set the Ethernet frame size to 9000 bytes, data from Avalon® streaming interface sink directly pass through and does not required buffering. You must assert avst_sink_valid continuously between the assertions of avst_sink_sop and avst_sink_eop. The only exception is when avst_sink_ready signal deasserts, and you are required to deassert avst_sink_valid for three cycles of READY_LATENCY.

The second L2 CoS priority arbitration is based on the ORAN-WG4.CUS.0-v07.01 specification, Section 5.3 Quality of Service, where the L2 CoS Priority of the packet determines the arbitration priority of the packet. You can enable this arbitration with Advance Mapping Mode. There are eight queues available to queue the packets for arbitration. Each queue is assigned with fixed priority 0 to 7, where queue 7 has the highest arbitration priority, and queue 0 has the lowest arbitration priority. Packets are stored into each queue according to the Priority Code Point (PCP) tag value extracted from the packet; for example, a packet with the PCP tag value of 7 is queued into queue 7.

The queue size for each priority must be configurable independently and use M20K to reduce ALM count. Queue depth must be configurable with a depth of 0/32/64/128/256 based on IP parameter selection per queue. The unused queue shall be configurable with the size of 0 to ensure no resource wastage. For queue 7, the minimum size is 32, and value 0 is not allowed to avoid a case where all queues are 0 sizes. When a particular queue size is configured to 0 (other than queue 7) and there is a request decoded with the PCP tag value of the queue, the request shall be routed to queue 7.

The ORAN C/U Plane packet uses the eCRPI IP Advance Mapping Mode feature to get the PCP value for the packet. When ORAN C/U Plane packet is sent into eCPRI IP, eCPRI IP uses the PCID sent as sideband and the packet to map to the VLAN tag register. The PCP values extracted from the VLAN tag register determine the queue to store the ORAN C/U Plane packet. The PCP field is a user input at packet SOP for S Plane, M-plane, and other traffic. Packets are stored in the queue according to the PCP field.

The PCP checker arbitrates the traffic (C/U/S/M/Other) based on the PCP tag value in the round-robin and stores it into the respective queue. Since the PTP software stack might not always generate PTP packets with the VLAN ID, the following statements explain the PCP values for handling each ITU-T profilethe the adetermine:

  • The first two profiles (8264 and 8275.1 profiles) – No VLAN ID (IP assigns the priority based on the TX Packets Default Priority parameter, default to highest 7).
  • The third profile (8275.2 profile) – parse PTP packet to extract PCP from L2/L3 header.
  • The primary use case is based on the L2 header and not the L3 header (8275.2 profile) – parser can parse the L2 header only to determine PTP packets and no L3 header parsing.

When the arbitration queue is full, backpressure applies to both eCPRI IP and S/M packets DCFIFO. Backpressure shall only apply on the same priority request. For example, when queue 7 is full, back pressure happens on traffic with PCP = 7 only (can be S/U/C/M plane traffic). Due to one input from ORAN IP for the U plane, subsequent packets with different priorities are blocked when the head of traffic is blocked. If the queue full happens in the middle of the packet, you must submit the remaining packet to the queue before switching to other traffic.

Run time priority change on traffic: You can switch PCP field values at packet boundary only, priority should remain the same for whole packet.

There is no starvation handling in hardware. For example, low-priority traffic always gives way to high-priority traffic and waits for its turn. Therefore, you are expected to handle the traffic flow between different queues to ensure no starvation scenarios which causes low-priority traffic continuously to get stuck in the queue without getting the arbitration grant.

Each queue generates FIFO full port and sends it to the eCPRI IP interface.

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