Native Loopback Accelerator Functional Unit (AFU) User Guide

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ID 683676
Date 8/05/2019
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. The Native Loopback Accelerator Functional Unit (AFU) 3. Document Revision History for the Native Loopback Accelerator Functional Unit (AFU) User Guide
1. About this Document x
1.1. Conventions 1.2. Acronyms 1.3. Acceleration Glossary
2. The Native Loopback Accelerator Functional Unit (AFU) x
2.1. Native Loopback (NLB) AFU Overview 2.2. The NLB Sample Accelerator Function (AF) 2.3. Native Loopback Control and Status Register Descriptions 2.4. Test Modes
2.4. Test Modes x
2.4.1. FPGA Diagnostics: fpgadiag 2.4.2. NLB Mode0 Hello_FPGA Test Flow
1. About this Document
2. The Native Loopback Accelerator Functional Unit (AFU)
3. Document Revision History for the Native Loopback Accelerator Functional Unit (AFU) User Guide

2.4.2. NLB Mode0 Hello_FPGA Test Flow

  1. Software initializes Device Status Memory (DSM) to zero.
  2. Software writes the DSM BASE address to the AFU.

    CSR Write(DSM_BASE_H), CSRWrite(DSM_BASE_L)

  3. Software prepares source and destination memory buffer. This preparation is test specific.
  4. Software writes CSR_CTL[2:0]= 0x1. This write brings the test out of reset and into configuration mode. Configuration can proceed only when CSR_CTL[0]=1 & CSR_CTL[1]=1.
  5. Software configures the test parameters, such as src, destaddress, csr_cfg, num lines, and so on.
  6. Software CSR writes CSR_CTL[2:0]= 0x3. The AF begins test execution.
  7. Test completion:
    • Hardware completes when the test completes or detects an error. Upon completion, the hardware AF updates DSM_STATUS. Software polls DSM_STATUS[31:0]==1 to detect test completion.
    • Software can force test completion by writing CSR writes CSR_CTL[2:0]=0x7. Hardware AF updates DSM_STATUS.
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