Native Loopback Accelerator Functional Unit (AFU) User Guide

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ID 683676
Date 8/05/2019
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. The Native Loopback Accelerator Functional Unit (AFU) 3. Document Revision History for the Native Loopback Accelerator Functional Unit (AFU) User Guide
1. About this Document x
1.1. Conventions 1.2. Acronyms 1.3. Acceleration Glossary
2. The Native Loopback Accelerator Functional Unit (AFU) x
2.1. Native Loopback (NLB) AFU Overview 2.2. The NLB Sample Accelerator Function (AF) 2.3. Native Loopback Control and Status Register Descriptions 2.4. Test Modes
2.4. Test Modes x
2.4.1. FPGA Diagnostics: fpgadiag 2.4.2. NLB Mode0 Hello_FPGA Test Flow
1. About this Document
2. The Native Loopback Accelerator Functional Unit (AFU)
3. Document Revision History for the Native Loopback Accelerator Functional Unit (AFU) User Guide

2.1. Native Loopback (NLB) AFU Overview

The NLB sample AFUs comprise a set of Verilog and System Verilog files to test memory reads and writes, bandwidth, and latency.

This package includes three AFUs that you can build from the same RTL source. Your configuration of the RTL source code creates these AFUs.

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