Visible to Intel only — GUID: aes1475017056754
Ixiasoft
1.4. Generating the Design
Figure 8. Procedure
Follow these steps to generate the hardware example design and testbench:
- In the Intel® Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new Intel® Quartus® Prime project, or click File > Open Project to open an existing Intel® Quartus® Prime project. The wizard prompts you to specify a device.
- Specify the device family Stratix 10 (GX/SX/MX/TX) and select device for your design.
- In the IP Catalog, locate and double-click Interlaken (2nd Generation) Intel FPGA IP. The New IP Variant window appears.
- Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
- Click OK. The parameter editor appears.
Figure 9. Example Design Tab in the Interlaken (2nd Generation) Intel® FPGA IP Parameter Editor
- On the IP tab, specify the parameters for your IP core variation.
- On the PMA Adaptation tab, specify the PMA adaptation parameters if you plan to use PMA adaptation for your E-tile device variations. This step is optional:
- Select Enable adaptation load soft IP option.
Note: You must enable Enable Native PHY Debug Master Endpoint (NPDME) option on the IP tab when PMA adaptation is enabled.
- Select a PMA adaptation preset for PMA adaptation Select parameter.
- Click PMA Adaptation Preload to load the initial and continuous adaptation parameters.
- Specify the number of PMA configurations to support when multiple PMA configurations are enabled using Number of PMA configuration parameter.
- Select which PMA configuration to load or store using Select a PMA configuration to load or store.
- Click Load adaptation from selected PMA configuration to load the selected PMA configuration settings.
- Select Enable adaptation load soft IP option.
- On the Example Design tab, select the Simulation option to generate the testbench, and select the Synthesis option to generate the hardware example design.
Note:
You must select at least one of the Simulation or Synthesis options generate the Example Design Files.
- For Generated HDL Format, only Verilog is available.
- For Target Development Kit select the appropriate option.
Note: The Intel® Stratix® 10 GX/TX Transceiver Signal Integrity Development Kit is only available when your project specifies Intel® Stratix® 10 device part number starting with:
- 1SG165H/1SG210H/1SG250H/1SG280H/1SX165H/1SX210H/1SX250H/1SX280H/1ST280E/1ST250E (For H-tile)
- ST280E/1ST250E (For E-tile)
- Click Generate Example Design. The Select Example Design Directory window appears.
- If you want to modify the design example directory path or name from the defaults displayed (uflex_ilk_0_example_design), browse to the new path and type the new design example directory name.
- Click OK.