Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683672
Date 8/03/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 4. Document Revision History for Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Directory Structure 1.3. Hardware Design Example Components 1.4. Generating the Design 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Interface Signals 2.3. Register Map
1. Quick Start Guide
2. Design Example Description
3. Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
4. Document Revision History for Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide

1.2. Directory Structure

The Interlaken (2nd Generation) IP core design example file directories contain the following generated files for the design example.
Figure 3. Directory Structure of the Generated Interlaken (2nd Generation) Example Design

The hardware configuration, simulation, and test files are located in

<design_example_installation_dir>/uflex_ilk_0_example_design.

Table 1.   Interlaken (2nd Generation) IP Core Hardware Design Example File DescriptionsThese files are in the <design_example_installation_dir>/uflex_ilk_0_example_design/example_design/quartus directory.
File Names Description
example_design.qpf Intel® Quartus® Prime project file.
example_design.qsf Intel® Quartus® Prime project settings file
example_design.sdc

jtag_timing_template.sdc

Synopsys Design Constraint file. You can copy and modify for your own design.
sysconsole_testbench.tcl Main file for accessing System Console
Table 2.   Interlaken (2nd Generation) IP Core Testbench File DescriptionThis file is in the <design_example_installation_dir>/uflex_ilk_0_example_design/example_design/rtl directory.
File Name Description
top_tb.sv Top-level testbench file.
Table 3.   Interlaken (2nd Generation) IP Core Testbench ScriptsThese files are in the <design_example_installation_dir>/uflex_ilk_0_example_design/example_design/testbench directory.
File Name Description
vcstest.sh The VCS* script to run the testbench.
vlog_pro.do The ModelSim* SE or QuestaSim* script to run the testbench.
xcelium.sh The Xcelium* script to run the testbench.
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