5G LDPC-V Intel® FPGA IP User Guide

ID 683670
Date 3/30/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.2. 5G LDPC-V Receiver Functional Description

The receiver comprises: a LDPC derate matcher, HARQ block, LDPC decoder, and LDPC code block segmentation CRC module.

LDPC derate matcher implements the rate recovery process, which is to reverse rate matching process. Refer to 3GPP Specification 38.212.

The HARQ block stores and combines derate matcher outputs from previous and current transmissions for LDPC decoder.

LDPC decoder implements the LDPC decode process, which is to reverse the LDPC encode process. Refer to 3GPP Specification 38.212.

The LDPC code block segmentation CRC module checks the 24-bit CRC embedded in the LDPC decoded bits. The LDPC code block segmentation CRC module. Refer to 3GPP Specification 38.212.