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1.4.3. Main Controller
The main controller is the heart of the design. The main controller instantiates the UFM which has an Avalon® Memory-Mapped (MM) Slave interface and controls all of the reading and writing to the UFM.
At power-up, the random start block issues a POR cycle and then sends a signal to the main data controller to read the UFM stored counter value at a static address and sends it to the 4-bit binary up-counter.
After the power-up fetch process completes, the main controller sits idle until the Reset signal is asserted or when it receives a signal from the 16-bit binary slow counter to initiate the power-down sequence.
When the main controller receives the power-down signal from the 16-bit binary slow counter, the main controller reads the current 4-bit binary up-counter value, removes the write protection of the UFM, writes the 4-bit binary up-counter value to the static address hard-coded in the design, turns back on the write protection for the UFM, and then sends the pwr_dwn_ready signal out of the device, which shuts off the power supply to the MAX 10 device.