L-Tile and H-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683667
Date 4/03/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.1.1.1.1. Read Data Mover

The Read Data module sends memory read TLPs. It writes the completion data to an external Avalon-MM interface through the high throughput Read Master port. This data mover operates on descriptors the IP core receives from the DMA Descriptor Controller.

Note: Completion TLPs for the Read Data Mover are restricted to a data payload of up to 256 bytes.

The Read DMA Avalon-MM Master interface performs the following functions:

1. Provides the Descriptor Table to the Descriptor Controller

The Read Data Mover sends PCIe* system memory read requests to fetch the descriptor table from PCIe* system memory. This module then writes the returned descriptor entries in to the Descriptor Controller FIFO using this Avalon-MM interface.

2. Writes Data to Memory Located in Avalon-MM Space

After a DMA Read finishes fetching data from the source address in PCIe* system memory, the Read Data Mover module writes the data to the destination address in Avalon-MM address space via this interface.

Table 29.  Read DMA 256-Bit Avalon-MM Master Interface

Signal Name

Direction

Description

rd_dma_write_o

Output

When asserted, indicates that the Read DMA module is ready to write read completion data to a memory component in the Avalon-MM address space.

rd_dma_address_o[63:0]

Output

Specifies the write address in the Avalon-MM address space for the read completion data.

rd_dma_write_data_o[255:0]

Output

The read completion data to be written to the Avalon-MM address space.

rd_dma_burst_count_o[4:0]

Output

Specifies the burst count in 256-bit words. This bus is 5 bits for the 256-bit interface.

rd_dma_byte_enable_o[31:0]

Output

Specifies which DWORDs are valid.

rd_dma_wait_request_i

Input

When asserted, indicates that the memory is not ready to receive data.

Figure 39. Read DMA Avalon-MM Master Writes Data to FPGA Memory