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1. Release Information
2. External Memory Interfaces Cyclone® 10 GX FPGA IP Introduction
3. Cyclone® 10 GX EMIF IP Product Architecture
4. Cyclone® 10 GX EMIF IP End-User Signals
5. Cyclone® 10 GX EMIF – Simulating Memory IP
6. Cyclone® 10 GX EMIF IP for DDR3
7. Cyclone® 10 GX EMIF IP for LPDDR3
8. Cyclone® 10 GX EMIF IP Timing Closure
9. Optimizing Controller Performance
10. Cyclone® 10 GX EMIF IP Debugging
11. External Memory Interfaces Cyclone® 10 GX FPGA IP User Guide Archives
12. Document Revision History for Cyclone® 10 GX External Memory Interfaces FPGA IP User Guide
4.1.1.1. pll_ref_clk for DDR3
4.1.1.2. pll_locked for DDR3
4.1.1.3. pll_extra_clk_0 for DDR3
4.1.1.4. pll_extra_clk_1 for DDR3
4.1.1.5. pll_extra_clk_2 for DDR3
4.1.1.6. pll_extra_clk_3 for DDR3
4.1.1.7. oct for DDR3
4.1.1.8. mem for DDR3
4.1.1.9. status for DDR3
4.1.1.10. afi_reset_n for DDR3
4.1.1.11. afi_clk for DDR3
4.1.1.12. afi_half_clk for DDR3
4.1.1.13. afi for DDR3
4.1.1.14. emif_usr_reset_n for DDR3
4.1.1.15. emif_usr_clk for DDR3
4.1.1.16. emif_usr_reset_n_sec for DDR3
4.1.1.17. emif_usr_clk_sec for DDR3
4.1.1.18. cal_debug_reset_n for DDR3
4.1.1.19. cal_debug_clk for DDR3
4.1.1.20. cal_debug_out_reset_n for DDR3
4.1.1.21. cal_debug_out_clk for DDR3
4.1.1.22. clks_sharing_master_out for DDR3
4.1.1.23. clks_sharing_slave_in for DDR3
4.1.1.24. clks_sharing_slave_out for DDR3
4.1.1.25. ctrl_amm for DDR3
4.1.1.26. ctrl_auto_precharge for DDR3
4.1.1.27. ctrl_user_priority for DDR3
4.1.1.28. ctrl_ecc_user_interrupt for DDR3
4.1.1.29. ctrl_ecc_readdataerror for DDR3
4.1.1.30. ctrl_mmr_slave for DDR3
4.1.1.31. cal_debug for DDR3
4.1.1.32. cal_debug_out for DDR3
4.1.2.1. pll_ref_clk for LPDDR3
4.1.2.2. pll_locked for LPDDR3
4.1.2.3. pll_extra_clk_0 for LPDDR3
4.1.2.4. pll_extra_clk_1 for LPDDR3
4.1.2.5. pll_extra_clk_2 for LPDDR3
4.1.2.6. pll_extra_clk_3 for LPDDR3
4.1.2.7. oct for LPDDR3
4.1.2.8. mem for LPDDR3
4.1.2.9. status for LPDDR3
4.1.2.10. afi_reset_n for LPDDR3
4.1.2.11. afi_clk for LPDDR3
4.1.2.12. afi_half_clk for LPDDR3
4.1.2.13. afi for LPDDR3
4.1.2.14. emif_usr_reset_n for LPDDR3
4.1.2.15. emif_usr_clk for LPDDR3
4.1.2.16. cal_debug_reset_n for LPDDR3
4.1.2.17. cal_debug_clk for LPDDR3
4.1.2.18. cal_debug_out_reset_n for LPDDR3
4.1.2.19. cal_debug_out_clk for LPDDR3
4.1.2.20. clks_sharing_master_out for LPDDR3
4.1.2.21. clks_sharing_slave_in for LPDDR3
4.1.2.22. clks_sharing_slave_out for LPDDR3
4.1.2.23. ctrl_user_priority for LPDDR3
4.1.2.24. ctrl_mmr_slave for LPDDR3
4.1.2.25. cal_debug for LPDDR3
4.1.2.26. cal_debug_out for LPDDR3
4.4.1. ctrlcfg0
4.4.2. ctrlcfg1
4.4.3. dramtiming0
4.4.4. sbcfg1
4.4.5. caltiming0
4.4.6. caltiming1
4.4.7. caltiming2
4.4.8. caltiming3
4.4.9. caltiming4
4.4.10. caltiming9
4.4.11. dramaddrw
4.4.12. sideband0
4.4.13. sideband1
4.4.14. sideband2
4.4.15. sideband3
4.4.16. sideband4
4.4.17. sideband5
4.4.18. sideband6
4.4.19. sideband7
4.4.20. sideband8
4.4.21. sideband9
4.4.22. sideband10
4.4.23. sideband11
4.4.24. sideband12
4.4.25. sideband13
4.4.26. dramsts
4.4.27. niosreserve0
4.4.28. niosreserve1
4.4.29. ecc3: ECC Error and Interrupt Configuration
4.4.30. ecc4: Status and Error Information
4.4.31. ecc5: Address of Most Recent SBE/DBE
4.4.32. ecc6: Address of Most Recent Correction Command Dropped
6.1.1. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: General
6.1.2. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: Memory
6.1.3. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: Mem I/O
6.1.4. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: FPGA I/O
6.1.5. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: Mem Timing
6.1.6. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: Board
6.1.7. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: Controller
6.1.8. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: Diagnostics
6.1.9. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: Example Designs
6.3.3.1. General Guidelines
6.3.3.2. x4 DIMM Implementation
Data Bus Connection Mapping Flow
Necessary checks to perform if the DQS groups are remapped in the RTL code
Necessary checks to perform if the DQS groups are remapped on the schematic
6.3.3.3. Command and Address Signals
6.3.3.4. Clock Signals
6.3.3.5. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3.3.6. Resource Sharing Guidelines (Multiple Interfaces)
6.3.3.7. Ping-Pong PHY Implementation
7.1.1. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: General
7.1.2. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Memory
7.1.3. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Mem I/O
7.1.4. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: FPGA I/O
7.1.5. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Mem Timing
7.1.6. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Board
7.1.7. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Controller
7.1.8. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Diagnostics
7.1.9. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Example Designs
9.4.1. Auto-Precharge Commands
9.4.2. Latency
9.4.3. Calibration
9.4.4. Bank Interleaving
9.4.5. Additive Latency and Bank Interleaving
9.4.6. User-Controlled Refresh
9.4.7. Frequency of Operation
9.4.8. Series of Reads or Writes
9.4.9. Data Reordering
9.4.10. Starvation Control
9.4.11. Command Reordering
9.4.12. Bandwidth
9.4.13. Enable Command Priority Control
10.1. Interface Configuration Performance Issues
10.2. Functional Issue Evaluation
10.3. Timing Issue Characteristics
10.4. Verifying Memory IP Using the Signal Tap II Logic Analyzer
10.5. Hardware Debugging Guidelines
10.6. Categorizing Hardware Issues
10.7. Debugging Cyclone® 10 GX EMIF IP
10.8. Using the Traffic Generator with the Generated Design Example
10.5.1. Create a Simplified Design that Demonstrates the Same Issue
10.5.2. Measure Power Distribution Network
10.5.3. Measure Signal Integrity and Setup and Hold Margin
10.5.4. Vary Voltage
10.5.5. Operate at a Lower Speed
10.5.6. Determine Whether the Issue Exists in Previous Versions of Software
10.5.7. Determine Whether the Issue Exists in the Current Version of Software
10.5.8. Try A Different PCB
10.5.9. Try Other Configurations
10.5.10. Debugging Checklist
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6.3.3.2. x4 DIMM Implementation
DIMMS using a x4 DQS configuration require remapping of the DQS signals to achieve compatibility between the EMIF IP and the JEDEC standard DIMM socket connections.
The necessary remapping is shown in the table below. You can implement this DQS remapping in either RTL logic or in your schematic wiring connections.
DIMM | Quartus® Prime EMIF IP | |||
---|---|---|---|---|
DQS0 | DQ[3:0] | DQS0 | DQ[3:0] | |
DQS9 | DQ[7:4] | DQS1 | DQ[7:4] | |
DQS1 | DQ[11:8] | DQS2 | DQ[11:8] | |
DQS10 | DQ[15:12] | DQS3 | DQ[15:12] | |
DQS2 | DQ[19:16] | DQS4 | DQ[19:16] | |
DQS11 | DQ[23:20] | DQS5 | DQ[23:20] | |
DQS3 | DQ[27:24] | DQS6 | DQ[27:24] | |
DQS12 | DQ[31:28] | DQS7 | DQ[31:28] | |
DQS4 | DQ[35:32] | DQS8 | DQ[35:32] | |
DQS13 | DQ[39:36] | DQS9 | DQ[39:36] | |
DQS5 | DQ[43:40] | DQS10 | DQ[43:40] | |
DQS14 | DQ[47:44] | DQS11 | DQ[47:44] | |
DQS6 | DQ[51:48] | DQS12 | DQ[51:48] | |
DQS15 | DQ[55:52] | DQS13 | DQ[55:52] | |
DQS7 | DQ[59:56] | DQS14 | DQ[59:56] | |
DQS16 | DQ[63:60] | DQS15 | DQ[63:60] | |
DQS8 | DQ[67:64] | DQS16 | DQ[67:64] | |
DQS17 | DQ[71:68] | DQS17 | DQ[71:68] |
Data Bus Connection Mapping Flow
- Connect all FPGA DQ pins accordingly to DIMM DQ pins. No remapping is required.
- DQS/DQSn remapping is required either on the board schematics or in the RTL code.
- An example mapping is shown below, with reference to the above table values:
FPGA (DQS0) to DIMM (DQS0) FPGA (DQS1) to DIMM (DQS9) FPGA (DQS2) to DIMM (DQS1) ... FPGA (DQS16) to DIMM (DQS8) FPGA (DQS17) to DIMM (DQS17)
When designing a board to support x4 DQS groups, Intel® recommends that you make it compatible for x8 mode, for the following reasons:
- Provides the flexibility of x4 and x8 DIMM support.
- Allows use of x8 DQS group connectivity rules.
- Allows use of x8 timing rules for matching. Intel® strongly recommends adhering to x4/x8 interoperability rules when designing a DIMM interface, even if the primary use case is to support x4 DIMMs only, because doing so facilitates debug and future migration capabilities. Regardless, the rules for length matching for two nibbles in a x4 interface must match those of the signals for a corresponding x8 interface, as the data terminations are turned on and off at the same time for both x4 DQS groups in an I/O lane. If the two x4 DQS groups were to have significantly different trace delays, it could adversely affect signal integrity.
Necessary checks to perform if the DQS groups are remapped in the RTL code
- In the Pin Planner, view x8 DQS groups and check the following:
- Check that DQ[7:0] is in x8 group, DQ[15:8] is in another DQS group, and so forth.
- Check that DSQ0 and DQS9 are in the DQS group with DQ[7:0], DQS1 and DQS10 are in the DQS group with DQ[15:8], and so forth. This is the DIMM numbering convention column shown in the table at the beginning of this topic.
- In the Pin Planner, view x4 DQS groups and check the following:
- Check that all the DQS signals are on pins marked S and Sbar.
- On the schematic, check the following DIMM connections:
- Check that DQSx on the DIMM maps to the DQSx on the FPGA pinout (for values of x from 0 to 17).
- Check that DQy on the DIMM maps to the DQy on the FPGA pinout. Note that there is scope for swapping pins within the x4 /x8 DQS group to optimize the PCB layout.
Necessary checks to perform if the DQS groups are remapped on the schematic
- In the Pin Planner, view x8 DQS groups and check the following:
- Check that DQ[7:0] is in x8 group, DQ[15:8] is in another DQS group, and so forth.
- Check that DSQ0 and DQS1 are in the DQS group with DQ[7:0], DQS2 and DQS3 are in the DQS group with DQ[15:8], and so forth. This is the Quartus® Prime EMIF IP mapping shown in the table at the beginning of this topic.
- In the Pin Planner, view x4 DQS groups and check the following:
- Check that all the DQS signals are on pins marked S and Sbar.
- On the schematic, check the following DIMM connections:
- Referring to the table above, check that DQS has the remapping between the FPGA ( Quartus® Prime EMIF IP) and DIMM pinout (DIMM).
- Check that DQy on the DIMM maps to the DQy on the FPGA pinout. Note that there is scope for swapping pins within the x4 /x8 DQS group to optimize the PCB layout.