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1. Release Information
2. External Memory Interfaces Cyclone® 10 GX FPGA IP Introduction
3. Cyclone® 10 GX EMIF IP Product Architecture
4. Cyclone® 10 GX EMIF IP End-User Signals
5. Cyclone® 10 GX EMIF – Simulating Memory IP
6. Cyclone® 10 GX EMIF IP for DDR3
7. Cyclone® 10 GX EMIF IP for LPDDR3
8. Cyclone® 10 GX EMIF IP Timing Closure
9. Optimizing Controller Performance
10. Cyclone® 10 GX EMIF IP Debugging
11. External Memory Interfaces Cyclone® 10 GX FPGA IP User Guide Archives
12. Document Revision History for Cyclone® 10 GX External Memory Interfaces FPGA IP User Guide
4.1.1.1. pll_ref_clk for DDR3
4.1.1.2. pll_locked for DDR3
4.1.1.3. pll_extra_clk_0 for DDR3
4.1.1.4. pll_extra_clk_1 for DDR3
4.1.1.5. pll_extra_clk_2 for DDR3
4.1.1.6. pll_extra_clk_3 for DDR3
4.1.1.7. oct for DDR3
4.1.1.8. mem for DDR3
4.1.1.9. status for DDR3
4.1.1.10. afi_reset_n for DDR3
4.1.1.11. afi_clk for DDR3
4.1.1.12. afi_half_clk for DDR3
4.1.1.13. afi for DDR3
4.1.1.14. emif_usr_reset_n for DDR3
4.1.1.15. emif_usr_clk for DDR3
4.1.1.16. emif_usr_reset_n_sec for DDR3
4.1.1.17. emif_usr_clk_sec for DDR3
4.1.1.18. cal_debug_reset_n for DDR3
4.1.1.19. cal_debug_clk for DDR3
4.1.1.20. cal_debug_out_reset_n for DDR3
4.1.1.21. cal_debug_out_clk for DDR3
4.1.1.22. clks_sharing_master_out for DDR3
4.1.1.23. clks_sharing_slave_in for DDR3
4.1.1.24. clks_sharing_slave_out for DDR3
4.1.1.25. ctrl_amm for DDR3
4.1.1.26. ctrl_auto_precharge for DDR3
4.1.1.27. ctrl_user_priority for DDR3
4.1.1.28. ctrl_ecc_user_interrupt for DDR3
4.1.1.29. ctrl_ecc_readdataerror for DDR3
4.1.1.30. ctrl_mmr_slave for DDR3
4.1.1.31. cal_debug for DDR3
4.1.1.32. cal_debug_out for DDR3
4.1.2.1. pll_ref_clk for LPDDR3
4.1.2.2. pll_locked for LPDDR3
4.1.2.3. pll_extra_clk_0 for LPDDR3
4.1.2.4. pll_extra_clk_1 for LPDDR3
4.1.2.5. pll_extra_clk_2 for LPDDR3
4.1.2.6. pll_extra_clk_3 for LPDDR3
4.1.2.7. oct for LPDDR3
4.1.2.8. mem for LPDDR3
4.1.2.9. status for LPDDR3
4.1.2.10. afi_reset_n for LPDDR3
4.1.2.11. afi_clk for LPDDR3
4.1.2.12. afi_half_clk for LPDDR3
4.1.2.13. afi for LPDDR3
4.1.2.14. emif_usr_reset_n for LPDDR3
4.1.2.15. emif_usr_clk for LPDDR3
4.1.2.16. cal_debug_reset_n for LPDDR3
4.1.2.17. cal_debug_clk for LPDDR3
4.1.2.18. cal_debug_out_reset_n for LPDDR3
4.1.2.19. cal_debug_out_clk for LPDDR3
4.1.2.20. clks_sharing_master_out for LPDDR3
4.1.2.21. clks_sharing_slave_in for LPDDR3
4.1.2.22. clks_sharing_slave_out for LPDDR3
4.1.2.23. ctrl_user_priority for LPDDR3
4.1.2.24. ctrl_mmr_slave for LPDDR3
4.1.2.25. cal_debug for LPDDR3
4.1.2.26. cal_debug_out for LPDDR3
4.4.1. ctrlcfg0
4.4.2. ctrlcfg1
4.4.3. dramtiming0
4.4.4. sbcfg1
4.4.5. caltiming0
4.4.6. caltiming1
4.4.7. caltiming2
4.4.8. caltiming3
4.4.9. caltiming4
4.4.10. caltiming9
4.4.11. dramaddrw
4.4.12. sideband0
4.4.13. sideband1
4.4.14. sideband2
4.4.15. sideband3
4.4.16. sideband4
4.4.17. sideband5
4.4.18. sideband6
4.4.19. sideband7
4.4.20. sideband8
4.4.21. sideband9
4.4.22. sideband10
4.4.23. sideband11
4.4.24. sideband12
4.4.25. sideband13
4.4.26. dramsts
4.4.27. niosreserve0
4.4.28. niosreserve1
4.4.29. ecc3: ECC Error and Interrupt Configuration
4.4.30. ecc4: Status and Error Information
4.4.31. ecc5: Address of Most Recent SBE/DBE
4.4.32. ecc6: Address of Most Recent Correction Command Dropped
6.1.1. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: General
6.1.2. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: Memory
6.1.3. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: Mem I/O
6.1.4. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: FPGA I/O
6.1.5. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: Mem Timing
6.1.6. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: Board
6.1.7. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: Controller
6.1.8. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: Diagnostics
6.1.9. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: Example Designs
7.1.1. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: General
7.1.2. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Memory
7.1.3. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Mem I/O
7.1.4. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: FPGA I/O
7.1.5. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Mem Timing
7.1.6. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Board
7.1.7. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Controller
7.1.8. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Diagnostics
7.1.9. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Example Designs
9.4.1. Auto-Precharge Commands
9.4.2. Latency
9.4.3. Calibration
9.4.4. Bank Interleaving
9.4.5. Additive Latency and Bank Interleaving
9.4.6. User-Controlled Refresh
9.4.7. Frequency of Operation
9.4.8. Series of Reads or Writes
9.4.9. Data Reordering
9.4.10. Starvation Control
9.4.11. Command Reordering
9.4.12. Bandwidth
9.4.13. Enable Command Priority Control
10.1. Interface Configuration Performance Issues
10.2. Functional Issue Evaluation
10.3. Timing Issue Characteristics
10.4. Verifying Memory IP Using the Signal Tap II Logic Analyzer
10.5. Hardware Debugging Guidelines
10.6. Categorizing Hardware Issues
10.7. Debugging Cyclone® 10 GX EMIF IP
10.8. Using the Traffic Generator with the Generated Design Example
10.5.1. Create a Simplified Design that Demonstrates the Same Issue
10.5.2. Measure Power Distribution Network
10.5.3. Measure Signal Integrity and Setup and Hold Margin
10.5.4. Vary Voltage
10.5.5. Operate at a Lower Speed
10.5.6. Determine Whether the Issue Exists in Previous Versions of Software
10.5.7. Determine Whether the Issue Exists in the Current Version of Software
10.5.8. Try A Different PCB
10.5.9. Try Other Configurations
10.5.10. Debugging Checklist
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7.1.5. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Mem Timing
These parameters should be read from the table in the datasheet associated with the speed bin of the memory device (not necessarily the frequency at which the interface is running).
Display Name | Description |
---|---|
Speed bin | The speed grade of the memory device used. This parameter refers to the maximum rate at which the memory device is specified to run. (Identifier: MEM_LPDDR3_SPEEDBIN_ENUM) |
tISCA (base) | Address and control setup to CK clock rise (Identifier: MEM_LPDDR3_TIS_PS) |
tISCA (base) AC level | AC level of tIS (base) for derating purpose (Identifier: MEM_LPDDR3_TIS_AC_MV) |
tIHCA (base) | Address and control hold after CK clock rise (Identifier: MEM_LPDDR3_TIH_PS) |
tIHCA (base) DC level | DC level of tIH (base) for derating purpose (Identifier: MEM_LPDDR3_TIH_DC_MV) |
tDS (base) | tDS(base) refers to the setup time for the Data (DQ) bus before the rising edge of the DQS strobe. (Identifier: MEM_LPDDR3_TDS_PS) |
tDS (base) AC level | tDS (base) AC level refers to the voltage level which the data bus must cross and remain above during the setup margin window. The signal is considered stable only if it remains above this voltage level (for a logic 1) or below this voltage level (for a logic 0) for the entire setup period. (Identifier: MEM_LPDDR3_TDS_AC_MV) |
tDH (base) | tDH (base) refers to the hold time for the Data (DQ) bus after the rising edge of CK. (Identifier: MEM_LPDDR3_TDH_PS) |
tDH (base) DC level | tDH (base) DC level refers to the voltage level which the data bus must not cross during the hold window. The signal is considered stable only if it remains above this voltage level (for a logic 1) or below this voltage level (for a logic 0) for the entire hold period. (Identifier: MEM_LPDDR3_TDH_DC_MV) |
tDQSQ | tDQSQ describes the latest valid transition of the associated DQ pins for a READ. tDQSQ specifically refers to the DQS, DQS# to DQ skew. It is the length of time between the DQS, DQS# crossing to the last valid transition of the slowest DQ pin in the DQ group associated with that DQS strobe. (Identifier: MEM_LPDDR3_TDQSQ_PS) |
tQH | tQH specifies the output hold time for the DQ in relation to DQS, DQS#. It is the length of time between the DQS, DQS# crossing to the earliest invalid transition of the fastest DQ pin in the DQ group associated with that DQS strobe. (Identifier: MEM_LPDDR3_TQH_CYC) |
tDQSCKDL | Absolute difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence of bursts within a 32ms rolling window (Identifier: MEM_LPDDR3_TDQSCKDL) |
tDQSS (max) | First latching edge of DQS to associated clock edge (percentage of tCK) (Identifier: MEM_LPDDR3_TDQSS_CYC) |
tQSH | tQSH refers to the differential High Pulse Width, which is measured as a percentage of tCK. It is the time during which the DQS is high for a read. (Identifier: MEM_LPDDR3_TQSH_CYC) |
tDSH | tDSH specifies the write DQS hold time. This is the time difference between the rising CK edge and the falling edge of DQS, measured as a percentage of tCK. (Identifier: MEM_LPDDR3_TDSH_CYC) |
tWLS | tWLS describes the write leveling setup time. It is measured from the rising edge of CK to the rising edge of DQS. (Identifier: MEM_LPDDR3_TWLS_PS) |
tWLH | tWLH describes the write leveling hold time. It is measured from the rising edge of DQS to the rising edge of CK. (Identifier: MEM_LPDDR3_TWLH_PS) |
tDSS | tDSS describes the time between the falling edge of DQS to the rising edge of the next CK transition. (Identifier: MEM_LPDDR3_TDSS_CYC) |
tINIT | tINIT describes the time duration of the memory initialization after a device power-up. After RESET_n is de-asserted, wait for another 500us until CKE becomes active. During this time, the DRAM will start internal initialization; this will be done independently of external clocks. (Identifier: MEM_LPDDR3_TINIT_US) |
tMRR | tMRR describes the minimum MODE REGISTER READ command period. (Identifier: MEM_LPDDR3_TMRR_CK_CYC) |
tMRW | tMRW describes the minimum MODE REGISTER WRITE command period. (Identifier: MEM_LPDDR3_TMRW_CK_CYC) |
tRAS | tRAS describes the activate to precharge duration. A row cannot be deactivated until the tRAS time has been met. Therefore tRAS determines how long the memory has to wait after a activate command before a precharge command can be issued to close the row. (Identifier: MEM_LPDDR3_TRAS_NS) |
tRCD | tRCD, row command delay, describes the active to read/write time. It is the amount of delay between the activation of a row through the RAS command and the access to the data through the CAS command. (Identifier: MEM_LPDDR3_TRCD_NS) |
tRPpb | Precharge command period (per bank) (Identifier: MEM_LPDDR3_TRP_NS) |
tWR | tWR refers to the Write Recovery time. It specifies the amount of clock cycles needed to complete a write before a precharge command can be issued. (Identifier: MEM_LPDDR3_TWR_NS) |
Display Name | Description |
---|---|
tRRD | tRRD refers to the Row Active to Row Active Delay. It is the minimum time interval (measured in memory clock cycles) between two activate commands to rows in different banks in the same rank (Identifier: MEM_LPDDR3_TRRD_CYC) |
tFAW | tFAW refers to the four activate window time. It describes the period of time during which only four banks can be active. (Identifier: MEM_LPDDR3_TFAW_NS) |
tWTR | tWTR or Write Timing Parameter describes the delay from start of internal write transaction to internal read command, for accesses to the same bank. The delay is measured from the first rising memory clock edge after the last write data is received to the rising memory clock edge when a read command is received. (Identifier: MEM_LPDDR3_TWTR_CYC) |
tRTP | tRTP refers to the internal READ Command to PRECHARGE Command delay. It is the number of memory clock cycles that is needed between a read command and a precharge command to the same rank. (Identifier: MEM_LPDDR3_TRTP_CYC) |
Display Name | Description |
---|---|
tRFCab | Auto-refresh command interval (all banks) (Identifier: MEM_LPDDR3_TRFC_NS) |
tREFI | tREFI refers to the average periodic refresh interval. It is the maximum amount of time the memory can tolerate in between each refresh command (Identifier: MEM_LPDDR3_TREFI_US) |