External Memory Interfaces Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 11/28/2024
Public

Visible to Intel only — GUID: hco1416491965846

Ixiasoft

Document Table of Contents

10.4.1. Signals to Monitor with the Signal Tap II Logic Analyzer

This topic lists the memory controller signals you should consider analyzing for different memory interfaces. This list is not exhaustive, but is a starting point.

Monitor the following signals:

  • amm_addr
  • amm_rdata
  • amm_rdata_valid
  • amm_read_req
  • amm_ready
  • amm_wdata
  • amm_write_req
  • fail
  • pass
  • afi_cal_fail
  • afi_cal_success
  • test_complete
  • pnf_per_bit
  • rdata_reg
  • rdata_valid_reg
  • data_out
  • data_in
  • written_data_fifo|data_out
  • usequencer|state *
  • usequencer|phy_seq_rdata_valid
  • usequencer|phy_seq_read_fifo_q
  • usequencer|phy_read_increment_vfifo *
  • usequencer|phy_read_latency_counter
  • uread_datapath|afi_rdata_en
  • uread_datapath|afi_rdata_valid
  • uread_datapath|ddio_phy_dq