AN 496: Using the Internal Oscillator Intel® FPGA IP

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ID 683653
Date 4/01/2024
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Document Table of Contents x
Using the Internal Oscillator Intel® FPGA IP
Using the Internal Oscillator Intel® FPGA IP x
Internal Oscillators Using the Internal Oscillator in MAX® II and MAX® V Devices Using the Internal Oscillator in All Supported Devices (except MAX® II and MAX® V devices) Implementation Document Revision History for AN 496: Using the Internal Oscillator Intel® FPGA IP
Implementation x
Design Example 1: Targeting a MDN-82 Demo Board ( MAX® II Devices) Design Example 2: Targeting a MAX® V Device Development Kit
Using the Internal Oscillator Intel® FPGA IP

Using the Internal Oscillator in MAX® II and MAX® V Devices

The internal oscillator has a single input, oscena, and a single output, osc. To activate the internal oscillator, use oscena. When activated, a clock with the frequency is made available at the output. If oscena is driven low, the output of the internal oscillator is a constant high.

To create a variant of the Internal Oscillator Intel® FPGA IP, follow these steps:

  1. In the IP catalog, navigate to Library > Basic Functions > I/O.
  2. Double-click MAX II/MAX V oscillator.
  3. Select the oscillator output frequency in the Parameter Editor.
  4. The model files that must be included are listed in Simulation Libraries. Click Next.
  5. Select the files to be created. Click Finish.

The selected files are created and can be accessed from the output file folder. After the instantiation code is added to the file, the oscena input must be made as a wire and assigned as a logic value of “1” to enable the oscillator.

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