Internal Oscillators
Most designs require a clock for normal operation. You can use the Internal Oscillator Intel® FPGA IP for clock source in user design or debug purposes. With an internal oscillator, the supported Intel® devices do not require external clocking circuitry. For example, you can use the internal oscillator to meet the clocking requirement of an LCD controller, system management bus (SMBus) controller, or any other interfacing protocol, or to implement a pulse width modulator. This helps minimize component count and board space, and reduces the total cost of the system.
You can instantiate the internal oscillator without instantiating the user flash memory (UFM) by using the supported Intel® devices' oscillator IP core in the Quartus® Prime software for MAX® II and MAX® V devices. For MAX® 10 devices, the oscillators are separate from the UFM.
The oscillator’s output frequency, osc, is one-fourth of the undivided frequency of the internal oscillator.
Device | Output Clock from Internal Oscillator 1 (MHz) |
---|---|
MAX® II | 3.3 – 5.5 |
MAX® V | 3.9 – 5.3 |
MAX® 10 | 55 – 116 2, 35 – 77 3 |
Cyclone® III 4 | 80 (max) |
Cyclone® IV | 80 (max) |
Cyclone® V | 100 (max) |
Cyclone® 10 GX | 100 (max) |
Cyclone® 10 LP | 80 (max) |
Arria® II GX | 100 (max) |
Arria® V | 100 (max) |
Arria® 10 | 100 (max) |
Stratix® V | 100 (max) |
Stratix® 10 | 170 – 230 |
Agilex™ 5 | 160 – 230 |
Agilex™ 7 | 160 – 230 |
The internal oscillator is part of the Program Erase Control block, which controls the programming and erasing of the UFM. The data register holds the data to be sent or retrieved from the UFM. The address register holds the address from which data is retrieved or the address to which the data is written.
The internal oscillator for the UFM block is enabled when the ERASE, PROGRAM, and READ operation is executed.
Signal | Description |
---|---|
oscena | Use to enable the internal oscillator. Input high to enable the oscillator. |
osc/clkout 5 | Output of the internal oscillator. |