Low Latency 40G Ethernet Intel® FPGA IP Release Notes

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ID 683651
Date 11/25/2024
Public
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Document Table of Contents x
1. Low Latency 40G Ethernet Intel® FPGA IP Release Notes
1. Low Latency 40G Ethernet Intel® FPGA IP Release Notes x
1.1. Low Latency 40G Ethernet Intel® FPGA IP (intel_eth_e40) v4.0.0 1.2. Low Latency 40G Ethernet Intel® FPGA IP (intel_eth_e40) v3.0.0 1.3. Low Latency 40G Ethernet Intel® FPGA IP (intel_eth_e40) v1.0.0 1.4. Low Latency 40G Ethernet IP Core (alt_e40) v19.2.0 1.5. Low Latency 40G Ethernet IP Core (alt_e40) v17.1
1. Low Latency 40G Ethernet Intel® FPGA IP Release Notes

1.1. Low Latency 40G Ethernet Intel® FPGA IP (intel_eth_e40) v4.0.0

Table 1.  v4.0.0 2024.11.25
Quartus® Prime Version Description Impact
24.3 Added PCS+PMA mode under MAC options in IP GUI. When selected, the PCS interfaces with the client via 128-bit XLGMII datapath
Support for Agilex™ 5 D-Series is no longer restricted. —
Added support for Aldec Riviera simulator. —
Removed the Debug option Enable JTAG to Avalon Master Bridge in the IP GUI. —
Level Two Title