Low Latency 40G Ethernet Intel® FPGA IP Release Notes

ID 683651
Date 7/22/2024
Public

1.1. Low Latency 40G Ethernet Intel® FPGA IP (intel_eth_e40) v3.0.0

Table 1.  v3.0.0 2024.07.08
Quartus® Prime Version Description Impact
24.2
  • Added Analog Parameters tab in the IP GUI.
  • Added the Enable cdr dedicated clk option in the IP GUI.
  • Added support for Agilex™ 5 D-Series FPGAs.1
1 Device support for Agilex™ 5 D-Series FPGAs and SoCs in the Quartus® Prime Pro Edition software version 24.2 is restricted. To enable D-Series device support in your instance of the Quartus® Prime Pro Edition software, contact your regional Altera sales representative.