Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

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ID 683641
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Design Optimization Overview 3. Optimizing the Design Netlist 4. Netlist Optimizations and Physical Synthesis 5. Area Optimization 6. Timing Closure and Optimization 7. Analyzing and Optimizing the Design Floorplan 8. Using the ECO Compilation Flow 9. Intel® Quartus® Prime Pro Edition Design Optimization User Guide Archives A. Intel® Quartus® Prime Pro Edition User Guides
2. Design Optimization Overview x
2.1. Initial FPGA Device Considerations 2.2. Initial Compiler Settings 2.3. Optimization Trade-Offs and Limitations 2.4. Design Visualization and Optimization Tools 2.5. Design Optimization Overview Revision History
2.1. Initial FPGA Device Considerations x
2.1.1. Device Migration Considerations
2.2. Initial Compiler Settings x
2.2.1. Initial I/O Assignment Guidelines 2.2.2. Initial Timing Constraint Guidelines
2.3. Optimization Trade-Offs and Limitations x
2.3.1. Area Reduction Trade-Offs 2.3.2. Critical Path Delay Reduction Trade-Offs 2.3.3. Power Consumption Reduction Trade-Offs 2.3.4. Compilation Time Trade-Offs
2.4. Design Visualization and Optimization Tools x
2.4.1. Design Visualization Tools 2.4.2. Design Optimization Tools
3. Optimizing the Design Netlist x
3.1. When to Use the Netlist Viewers: Analyzing Design Problems 3.2. Intel® Quartus® Prime Design Flow with the Netlist Viewers 3.3. RTL Viewer Overview 3.4. Technology Map Viewer Overview 3.5. Netlist Viewer User Interface 3.6. Schematic View 3.7. Cross-Probing to a Source Design File and Other Intel® Quartus® Prime Windows 3.8. Cross-Probing to the Netlist Viewers from Other Intel® Quartus® Prime Windows 3.9. Viewing a Timing Path 3.10. Optimizing the Design Netlist Revision History
3.3. RTL Viewer Overview x
3.3.1. Maximizing Readability in RTL Viewer 3.3.2. Running the RTL Viewer
3.5. Netlist Viewer User Interface x
3.5.1. Netlist Navigator Pane 3.5.2. Properties Pane 3.5.3. Netlist Viewers Find Pane
3.6. Schematic View x
3.6.1. Display Schematics in Multiple Tabbed View 3.6.2. Schematic Symbols 3.6.3. Select Items in the Schematic View 3.6.4. Shortcut Menu Commands in the Schematic View 3.6.5. Filtering in the Schematic View 3.6.6. View Contents of Nodes in the Schematic View 3.6.7. Moving Nodes in the Schematic View 3.6.8. View LUT Representations in the Technology Map Viewer 3.6.9. Zoom Controls 3.6.10. Navigating with the Bird's Eye View 3.6.11. Partition the Schematic into Pages 3.6.12. Follow Nets Across Schematic Pages
4. Netlist Optimizations and Physical Synthesis x
4.1. Physical Synthesis Optimizations 4.2. Applying Netlist Optimizations 4.3. Scripting Support 4.4. Netlist Optimizations and Physical Synthesis Revision History
4.1. Physical Synthesis Optimizations x
4.1.1. Disabling or Enabling Physical Synthesis Optimization 4.1.2. Physical Synthesis Options
4.2. Applying Netlist Optimizations x
4.2.1. WYSIWYG Primitive Resynthesis
4.3. Scripting Support x
4.3.1. Synthesis Netlist Optimizations 4.3.2. Physical Synthesis Optimizations
5. Area Optimization x
5.1. Resource Utilization Information 5.2. Optimizing Resource Utilization 5.3. Scripting Support 5.4. Area Optimization Revision History
5.1. Resource Utilization Information x
5.1.1. Flow Summary Report 5.1.2. Fitter Reports 5.1.3. Design Assistant Recommendations 5.1.4. Analysis and Synthesis Reports 5.1.5. Compilation Messages 5.1.6. Chip Planner Visualization
5.2. Optimizing Resource Utilization x
5.2.1. Resource Utilization Issues Overview 5.2.2. I/O Pin Utilization or Placement 5.2.3. Logic Utilization or Placement 5.2.4. Routing
5.2.2. I/O Pin Utilization or Placement x
5.2.2.1. Guideline: Modify Pin Assignments or Choose a Larger Package
5.2.3. Logic Utilization or Placement x
5.2.3.1. Guideline: Optimize Source Code 5.2.3.2. Guideline: Optimize Synthesis for Area, Not Speed 5.2.3.3. Guideline: Restructure Multiplexers 5.2.3.4. Guideline: Perform WYSIWYG Primitive Resynthesis with Balanced or Area Setting 5.2.3.5. Guideline: Use Register Packing 5.2.3.6. Guideline: Remove Fitter Constraints 5.2.3.7. Guideline: Flatten the Hierarchy During Synthesis 5.2.3.8. Guideline: Re-target Memory Blocks 5.2.3.9. Guideline: Use Physical Synthesis Options to Reduce Area 5.2.3.10. Guideline: Retarget or Balance DSP Blocks 5.2.3.11. Guideline: Use a Larger Device 5.2.3.12. Guideline: Reduce Global Signal Congestion 5.2.3.13. Guideline: Report Pipelining Information
5.2.4. Routing x
5.2.4.1. Guideline: Set Auto Packed Registers to Sparse or Sparse Auto 5.2.4.2. Guideline: Set Fitter Aggressive Routability Optimizations to Always 5.2.4.3. Guideline: Increase Router Effort Multiplier 5.2.4.4. Guideline: Remove Fitter Constraints 5.2.4.5. Guideline: Optimize Synthesis for Routability 5.2.4.6. Guideline: Optimize Source Code 5.2.4.7. Guideline: Use a Larger Device
5.3. Scripting Support x
5.3.1. Initial Compilation Settings 5.3.2. Resource Utilization Optimization Techniques
6. Timing Closure and Optimization x
6.1. Optimize Multi Corner Timing 6.2. Optimize Critical Paths 6.3. Optimize Critical Chains 6.4. Design Evaluation for Timing Closure 6.5. Timing Optimization 6.6. Periphery to Core Register Placement and Routing Optimization 6.7. Scripting Support 6.8. Timing Closure and Optimization Revision History
6.2. Optimize Critical Paths x
6.2.1. Viewing Critical Paths
6.3. Optimize Critical Chains x
6.3.1. Viewing Critical Chains
6.4. Design Evaluation for Timing Closure x
6.4.1. Review Messages 6.4.2. Evaluate Fitter Netlist Optimizations 6.4.3. Evaluate Optimization Results 6.4.4. Evaluate Resource Usage 6.4.5. Evaluate Other Reports and Adjust Settings Accordingly 6.4.6. Evaluate Clustering Difficulty 6.4.7. Revise and Recompile
6.4.4. Evaluate Resource Usage x
6.4.4.1. Evaluate Global and Non-Global Usage 6.4.4.2. Evaluate Routing Usage 6.4.4.3. Evaluate Wires Added for Hold
6.5. Timing Optimization x
6.5.1. Correct Design Assistant Rule Violations 6.5.2. Implement Fast Forward Timing Closure Recommendations 6.5.3. Review Timing Path Details 6.5.4. Try Optional Fitter Settings 6.5.5. Back-Annotate Optimized Assignments 6.5.6. Optimize Settings with Design Space Explorer II 6.5.7. I/O Timing Optimization Techniques 6.5.8. Register-to-Register Timing Optimization Techniques 6.5.9. Metastability Analysis and Optimization Techniques
6.5.2. Implement Fast Forward Timing Closure Recommendations x
6.5.2.1. Retiming Limit Details Report 6.5.2.2. Fast Forward Timing Closure Recommendations
6.5.2.1. Retiming Limit Details Report x
6.5.2.1.1. Using the Retiming Limit Details Report
6.5.2.2. Fast Forward Timing Closure Recommendations x
6.5.2.2.1. Generating Fast Forward Timing Closure Recommendations 6.5.2.2.2. Implementing Fast Forward Recommendations
6.5.3. Review Timing Path Details x
6.5.3.1. Report Timing 6.5.3.2. Report Logic Depth 6.5.3.3. Report Neighbor Paths 6.5.3.4. Report Register Spread 6.5.3.5. Report Route Net of Interest 6.5.3.6. Report Retiming Restrictions 6.5.3.7. Report Pipelining Information 6.5.3.8. Report CDC Viewer 6.5.3.9. Timing Closure Recommendations 6.5.3.10. Global Network Buffers 6.5.3.11. Resets and Global Networks 6.5.3.12. Suspicious Setup 6.5.3.13. Auto Shift Register Replacement 6.5.3.14. Clocking Architecture
6.5.3.10. Global Network Buffers x
6.5.3.10.1. Source Location 6.5.3.10.2. Insertion Delay 6.5.3.10.3. Fan-Out 6.5.3.10.4. Global Signal Assignment
6.5.4. Try Optional Fitter Settings x
6.5.4.1. Optimize Hold Timing 6.5.4.2. Fitter Aggressive Routability Optimization
6.5.6. Optimize Settings with Design Space Explorer II x
6.5.6.1. DSE II Computing Resources 6.5.6.2. DSE II Optimization Parameters 6.5.6.3. DSE II Result Management 6.5.6.4. Running DSE II
6.5.7. I/O Timing Optimization Techniques x
6.5.7.1. I/O Timing Constraints 6.5.7.2. Optimize IOC Register Placement for Timing Logic Option 6.5.7.3. Fast Input, Output, and Output Enable Registers 6.5.7.4. Programmable Delays 6.5.7.5. Use PLLs to Shift Clock Edges 6.5.7.6. Use Fast Regional Clock Networks and Regional Clocks Networks 6.5.7.7. Spine Clock Limitations
6.5.8. Register-to-Register Timing Optimization Techniques x
6.5.8.1. Optimize Source Code 6.5.8.2. Improving Register-to-Register Timing 6.5.8.3. Physical Synthesis Optimizations 6.5.8.4. Set Power Optimization During Synthesis to Normal Compilation 6.5.8.5. Optimize Synthesis for Performance, Not Area 6.5.8.6. Flatten the Hierarchy During Synthesis 6.5.8.7. Set the Synthesis Effort to High 6.5.8.8. Duplicate Registers for Fan-Out Control 6.5.8.9. Prevent Shift Register Inference 6.5.8.10. Use Other Synthesis Options Available in Your Synthesis Tool 6.5.8.11. Fitter Seed 6.5.8.12. Set Maximum Router Timing Optimization Level 6.5.8.13. Register-to-Register Timing Analysis
6.5.8.8. Duplicate Registers for Fan-Out Control x
6.5.8.8.1. Manual Register Duplication 6.5.8.8.2. Automatic Register Duplication: Estimated Physical Proximity 6.5.8.8.3. Automatic Register Duplication: Hierarchical Proximity
6.5.8.13. Register-to-Register Timing Analysis x
6.5.8.13.1. Tips for Analyzing Failing Paths 6.5.8.13.2. Tips for Analyzing Failing Clock Paths that Cross Clock Domains 6.5.8.13.3. Tips for Critical Path Analysis 6.5.8.13.4. Tips for Creating a .tcl Script to Monitor Critical Paths Across Compiles 6.5.8.13.5. Global Routing Resources 6.5.8.13.6. Register RAMS and DSPs
6.6. Periphery to Core Register Placement and Routing Optimization x
6.6.1. Setting Periphery to Core Optimizations in the Advanced Fitter Setting Dialog Box 6.6.2. Setting Periphery to Core Optimizations in the Assignment Editor 6.6.3. Viewing Periphery to Core Optimizations in the Fitter Report
6.7. Scripting Support x
6.7.1. Initial Compilation Settings 6.7.2. I/O Timing Optimization Techniques 6.7.3. Register-to-Register Timing Optimization Techniques
7. Analyzing and Optimizing the Design Floorplan x
7.1. Design Floorplan Analysis in Chip Planner 7.2. Defining Logic Lock Placement Constraints 7.3. Defining Virtual Pins 7.4. Using Logic Lock Regions in Combination with Design Partitions 7.5. Creating Clock Region Assignments in Chip Planner 7.6. Scripting Support 7.7. Analyzing and Optimizing the Design Floorplan Revision History
7.1. Design Floorplan Analysis in Chip Planner x
7.1.1. Starting the Chip Planner 7.1.2. Chip Planner GUI 7.1.3. Viewing Design Elements in Chip Planner 7.1.4. Finding Design Elements in the Chip Planner 7.1.5. Exploring Paths in the Chip Planner 7.1.6. Viewing Assignments in the Chip Planner 7.1.7. Viewing High-Speed and Low-Power Tiles in the Chip Planner 7.1.8. Viewing Design Partition Placement
7.1.3. Viewing Design Elements in Chip Planner x
7.1.3.1. Viewing Architecture-Specific Design Information in Chip Planner 7.1.3.2. Viewing Available Clock Networks in Chip Planner 7.1.3.3. Viewing Clock Sector Utilization in Chip Planner 7.1.3.4. Viewing Routing Congestion in Chip Planner 7.1.3.5. Viewing I/O Banks in Chip Planner 7.1.3.6. Viewing High-Speed Serial Interfaces (HSSI) in Chip Planner 7.1.3.7. Viewing Source and Destination Nodes in Chip Planner 7.1.3.8. Viewing Fan-In and Fan-Out in Chip Planner 7.1.3.9. Viewing Immediate Fan-In and Fan-Out in Chip Planner 7.1.3.10. Viewing the Selected Contents in Chip Planner 7.1.3.11. Viewing the Location and Utilization of Device Resources in Chip Planner 7.1.3.12. Viewing Module Placement by Cross-Probing to Chip Planner
7.1.4. Finding Design Elements in the Chip Planner x
7.1.4.1. Find Options (Chip Planner Search)
7.1.5. Exploring Paths in the Chip Planner x
7.1.5.1. Analyzing Connections for a Path 7.1.5.2. Locate Path from the Timing Analysis Report to the Chip Planner 7.1.5.3. Show Delays 7.1.5.4. Viewing Routing Resources
7.2. Defining Logic Lock Placement Constraints x
7.2.1. The Logic Lock Regions Window 7.2.2. Defining Logic Lock Regions 7.2.3. Customizing the Shape of Logic Lock Regions 7.2.4. Assigning Device Pins to Logic Lock Regions 7.2.5. Viewing Connections Between Logic Lock Regions in Chip Planner 7.2.6. Example: Placement Best Practices for Intel® Arria® 10 FPGAs 7.2.7. Migrating Assignments between Intel® Quartus® Prime Standard Edition and Intel® Quartus® Prime Pro Edition
7.2.2. Defining Logic Lock Regions x
7.2.2.1. Defining a Logic Lock Region in Chip Planner 7.2.2.2. Defining a Logic Lock Region from the Project Navigator 7.2.2.3. Defining Routing Regions 7.2.2.4. Defining Empty Logic Lock Regions 7.2.2.5. Defining Hierarchical Logic Lock Regions
7.2.2.1. Defining a Logic Lock Region in Chip Planner x
7.2.2.1.1. Logic Lock Region Properties 7.2.2.1.2. Snapping to a Region 7.2.2.1.3. Considerations for Auto Sized Regions
7.2.3. Customizing the Shape of Logic Lock Regions x
7.2.3.1. Adding a New Shape to a Logic Lock Region 7.2.3.2. Subtracting Shape from Logic Lock Region 7.2.3.3. Merging Logic Lock Regions 7.2.3.4. Defining Noncontiguous Logic Lock Regions
7.4. Using Logic Lock Regions in Combination with Design Partitions x
7.4.1. Viewing Design Connectivity and Hierarchy
7.5. Creating Clock Region Assignments in Chip Planner x
7.5.1. Creating Clock Assignments in Chip Planner 7.5.2. Resizing a Clock Assignment in Chip Planner 7.5.3. Moving a Clock Assignment in Chip Planner 7.5.4. Deleting a Clock Region Assignment in Chip Planner 7.5.5. Assigning a Clock Signal to a Clock Region in Chip Planner
7.5.1. Creating Clock Assignments in Chip Planner x
7.5.1.1. Clock Assignment Properties
7.6. Scripting Support x
7.6.1. Creating Logic Lock Assignments with Tcl commands 7.6.2. Assigning Virtual Pins with a Tcl command 7.6.3. Logic Lock Region Assignment Examples
8. Using the ECO Compilation Flow x
8.1. ECO Compilation Flow 8.2. ECO Tcl Script Example 8.3. Viewing ECO Compilation Reports 8.4. ECO Commands 8.5. ECO Command Limitations 8.6. Interactive ECO Fitting 8.7. Using the ECO Compilation Flow Revision History
8.4. ECO Commands x
8.4.1. ECO Command Quick Reference 8.4.2. make_connection 8.4.3. remove_connection 8.4.4. modify_lutmask 8.4.5. adjust_pll_refclk 8.4.6. modify_io_slew_rate 8.4.7. modify_io_current_strength 8.4.8. modify_io_delay_chain 8.4.9. create_new_node 8.4.10. remove_node 8.4.11. place_node 8.4.12. unplace_node 8.4.13. create_wirelut
8.6. Interactive ECO Fitting x
8.6.1. eco_load_design and eco_commit_design Commands
1. Answers to Top FAQs
2. Design Optimization Overview
3. Optimizing the Design Netlist
4. Netlist Optimizations and Physical Synthesis
5. Area Optimization
6. Timing Closure and Optimization
7. Analyzing and Optimizing the Design Floorplan
8. Using the ECO Compilation Flow
9. Intel® Quartus® Prime Pro Edition Design Optimization User Guide Archives
A. Intel® Quartus® Prime Pro Edition User Guides

6.8. Timing Closure and Optimization Revision History

The following revision history applies to this chapter:

Document Version Intel® Quartus® Prime Version Changes
2022.01.07 21.4
  • Clarified device applicability in Spine Clock Limitations topic.
  • Added Design Assistant information to Review Timing Constraints topic.
  • Added Design Assistant information to Review Timing Constraints topic.
  • Removed references to obsolete Advisors throughout.
  • Added Design Assistant information to Optimize Source Code topic.
  • Added Design Assistant information to Improving Register-to-Register Timing topic.
  • Added Design Assistant information to Optimize Synthesis for Performance, Not Area topic.
  • Added set_clock_groups -exclusive setting information to Tips for Analyzing Failing Clock Paths that Cross Clock Domains topic.
  • Added new Register RAMS and DSPs topic.
  • Revised Metastability Analysis and Optimization Techniques topic for synchronizers.
2021.10.04 21.3
  • Updated name of Report Hierarchical Retiming Restrictions command and report to Report Retiming Restrictions.
2021.06.21 21.2
  • Added note about variables that can cause differences in the compilation results between seed sweeps with DSE II.
2020.09.28 20.3
  • Added "Back-Annotate Optimized Assignments" topic to describe new GUI support for back-annotation of pin, RAM, DSP, and clock assignments.
  • Added "Correct Design Assistant Rule Violations" topic.
  • Updated "Report Timing" topic for Extra Info tab data.
  • Added new "Report Logic Depth," "Report Neighbor Paths, "Report Register Spread," "Report Route Net of Interest," "Report Hierarchical Retiming Restrictions," and "Report Pipelining Information," topics to "Review Details of Timing Paths" section.
  • Moved "Optimize Settings with Design Space Explorer II" to "Design Evaluation for Timing Closure" section and updated links to Help.
  • Retitled "Intel Stratix 10 Timing Closure Recommendations" topic to "Implement Fast Forward Timing Closure Recommendations".
2019.07.01 19.1 Added important notes to Automatic Register Duplication: Estimated Physical Proximity and Automatic Register Duplication: Hierarchical Proximity topics.
2019.04.01 19.1
  • Added more information about register duplication methods in Duplicate Logic for Fan-out Control topic.
  • Moved content related to manual register duplication from Duplicate Logic for Fan-out Control topic to a newly created sub-topic Manually Adding Duplicate Registers.
  • Added Automatic Register Duplication: Estimated Physical Proximity and Automatic Register Duplication: Hierarchical Proximity as new sub-topics under Duplicate Logic for Fan-out Control to describe automatic register duplication process.
2018.11.12 18.1.0
  • Updated "Placement Effort Multiplier" figure and text descriptions in "Adjust Placement Effort" topic.
  • Updated "Fitter Effort" figure and text descriptions in "Adjust Fitter Effort" topic.
  • Updated "Optimize Hold Timing Option" screenshot in "Wires Added for Hold" topic.
2018.09.24 18.1.0
  • Removed duplicated topic: Resource Utilization Optimization Techniques. The topic is now in the Area Optimization chapter.
  • Removed reference to unsupported CARRY and CASCADE buffers from "Optimize IOC Register Placement for Timing Logic Option" topic.
2017.11.06 17.1.0
  • Added support for Intel® Stratix® 10 Hyper-Retiming, Fast Forward compilation, and Fast Forward Viewer.
    • Added topics: Critical Chains, Viewing Critical Chains, Intel Stratix 10 Timing Closure Recommendations, Retiming Limit Details Report, Using the Retiming Limit Details Report, Fast Forward Timing Closure Recommendations, Generating Fast Forward Timing Closure Recommendations, Implementing Fast Forward Recommendations.
  • Added topic about using partitions to achieve timing closure.
  • Moved Topic: Design Evaluation for Timing Closure after Initial Compilation: Optional Fitter Settings.
  • Removed statement about applying physical synthesis optimizations in a portion of a design.
  • Removed references to optimizing hold timing for selected paths.
  • Updated logic options about resource utilization optimization settings.
2017.05.08 17.0.0
  • Added topic: Critical Paths.
  • Updated Register-to-Register Timing and renamed to Register-to-Register Timing Analysis.
  • Renamed topic: Timing Analysis with the Timing Analyzer to Displaying Path Reports with the Timing Analyzer.
  • Removed (LUT-Based Devices) remark from topic titles.
  • Renamed topic: Optimizing Timing (LUT-Based Devices) to Timing Optimization.
  • Renamed topic: Debugging Timing Failures in the Timing Analyzer to Displaying Timing Closure Recommendations for Failing Paths.
  • Renamed topic: Improving Register-to-Register Timing Summary to Improving Register-to-Register Timing .
  • Removed topics: Tips for Locating Multiple Paths to the Chip Planner, LogicLock Assignments and Hierarchy Assignments, .
  • Removed reference to deprecated Fitter Effort Logic Option.
  • Removed information about Pin Advisor and Resource Optimization Advisor.
  • Removed figure: Clock Regions
2016.10.31 16.1.0
  • Implemented Intel rebranding.
2016.05.02 16.0.0
  • Removed information about deprecated physical synthesis options.
  • Added information about monitoring clustering difficulty.
2015.11.02 15.1.0
  • Added: Periphery to Core Register Placement and Routing Optimization.
  • Changed instances of Quartus II to Quartus Prime.
2014.12.15 14.1.0
  • Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Synthesis Optimizations to Compiler Settings.
  • Updated DSE II content.
June 2014 14.0.0
  • Dita conversion.
  • Removed content about obsolete devices that are no longer supported in QII software v14.0: Arria GX, Arria II, Cyclone III, Stratix II, Stratix III.
  • Replaced Megafunction content with IP core content.
November 2013 13.1.0
  • Added Design Evaluation for Timing Closure section.
  • Removed Optimizing Timing (Macrocell-Based CPLDs) section.
  • Updated Optimize Multi-Corner Timing and Fitter Aggressive Routability Optimization.
  • Updated Timing Analysis with the Timing Analyzer to show how to access the Report All Summaries command.
  • Updated Ignored Timing Constraints to include a help link to Fitter Summary Reports with the Ignored Assignment Report information.
May 2013 13.0.0
  • Renamed chapter title from Area and Timing Optimization to Timing Closure and Optimization.
  • Removed design and area/resources optimization information.
  • Added the following sections:

    Fitter Aggressive Routability Optimization.

    Tips for Analyzing Paths from/to the Source and Destination of Critical Path.

    Tips for Locating Multiple Paths to the Chip Planner.

    Tips for Creating a .tcl Script to Monitor Critical Paths Across Compiles.

November 2012 12.1.0
  • Updated “Initial Compilation: Optional Fitter Settings” on page 13–2, “I/O Assignments” on page 13–2, “Initial Compilation: Optional Fitter Settings” on page 13–2, “Resource Utilization” on page 13–9, “Routing” on page 13–21, and “Resolving Resource Utilization Problems” on page 13–43.
June 2012 12.0.0
  • Updated “Optimize Multi-Corner Timing” on page 13–6, “Resource Utilization” on page 13–10, “Timing Analysis with the Timing Analyzer” on page 13–12, “Using the Resource Optimization Advisor” on page 13–15, “Increase Placement Effort Multiplier” on page 13–22, “Increase Router Effort Multiplier” on page 13–22 and “Debugging Timing Failures in the Timing Analyzer” on page 13–24.
  • Minor text edits throughout the chapter.
November 2011 11.1.0
  • Updated the “Timing Requirement Settings”, “Standard Fit”, “Fast Fit”, “Optimize Multi-Corner Timing”, “Timing Analysis with the Timing Analyzer”, “Debugging Timing Failures in the Timing Analyzer”, “LogicLock Assignments”, “Tips for Analyzing Failing Clock Paths that Cross Clock Domains”, “Flatten the Hierarchy During Synthesis”, “Fast Input, Output, and Output Enable Registers”, and “Hierarchy Assignments” sections
  • Updated Table 13–6
  • Added the “Spine Clock Limitations” section
  • Removed the Change State Machine Encoding section from page 19
  • Removed Figure 13-5
  • Minor text edits throughout the chapter
May 2011 11.0.0
  • Reorganized sections in “Initial Compilation: Optional Fitter Settings” section
  • Added new information to “Resource Utilization” section
  • Added new information to “Duplicate Logic for Fan-Out Control” section
  • Added links to Help
  • Additional edits and updates throughout chapter
December 2010 10.1.0
  • Added links to Help
  • Updated device support
  • Added “Debugging Timing Failures in the Timing Analyzer” section
  • Removed Classic Timing Analyzer references
  • Other updates throughout chapter
August 2010 10.0.1 Corrected link
July 2010 10.0.0
  • Moved Compilation Time Optimization Techniques section to new Reducing Compilation Time chapter
  • Removed references to Timing Closure Floorplan
  • Moved Smart Compilation Setting and Early Timing Estimation sections to new Reducing Compilation Time chapter
  • Added Other Optimization Resources section
  • Removed outdated information
  • Changed references to DSE chapter to Help links
  • Linked to Help where appropriate
  • Removed Referenced Documents section
Level Two Title