AN 886: Intel Agilex® 7 Device Design Guidelines

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ID 683634
Date 10/09/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction to the Intel Agilex® 7 Device Design Guidelines 2. System Specification 3. Device Selection 4. Security Considerations 5. Design Entry 6. Board and Software Considerations 7. Design Implementation, Analysis, Optimization, and Verification 8. Debugging 9. Embedded Software Design Guidelines for Intel Agilex® 7 SoC FPGAs
1. Introduction to the Intel Agilex® 7 Device Design Guidelines x
1.1. Design Flow 1.2. Introduction to the Intel Agilex® 7 Device Design Guidelines Revision History
2. System Specification x
2.1. Design Specifications 2.2. Install Intel® Quartus® Prime Software 2.3. IP Selection 2.4. Simulation 2.5. Preparing for Design Entry 2.6. I/O Summary 2.7. Using Intel Agilex® 7 HPS in your Device 2.8. System Specification Revision History
2.3. IP Selection x
2.3.1. Evaluate Available HPS IP 2.3.2. Select Soft/Hardened IP and I/O Interfaces
2.5. Preparing for Design Entry x
2.5.1. Coding Styles and Design Recommendations 2.5.2. Platform Designer
3. Device Selection x
3.1. Device Variant 3.2. PLLs and Clock Routing 3.3. Logic, Memory, and Multiplier Density 3.4. I/O Pin Count, LVDS SERDES Channels, and Package Offering 3.5. Speed Grade 3.6. Device Migration 3.7. Device Selection Revision History
4. Security Considerations x
4.1. Security Considerations Revision History
5. Design Entry x
5.1. Design Entry for SoC Devices 5.2. Design Entry for FPGA-only Devices 5.3. Design Entry for NoC 5.4. EMIF Considerations 5.5. Nios® Software Processor IP 5.6. Transceiver Planning 5.7. Reconfiguration 5.8. Design Entry Revision History
5.1. Design Entry for SoC Devices x
5.1.1. Firewall Planning 5.1.2. Boot And Configuration Considerations 5.1.3. HPS Clocking and Reset Design Considerations 5.1.4. Reset Configuration 5.1.5. HPS Pin Multiplexing Design Considerations 5.1.6. HPS I/O Settings: Constraints and Drive Strengths 5.1.7. Design Guidelines for HPS Interfaces 5.1.8. Interfacing between the FPGA and HPS 5.1.9. Implementing the Intel Agilex® 7 HPS Component
5.1.2. Boot And Configuration Considerations x
5.1.2.1. Selecting HPS Boot Options 5.1.2.2. Configuration Sources 5.1.2.3. Remote System Update (RSU)
5.1.3. HPS Clocking and Reset Design Considerations x
5.1.3.1. HPS Clock Planning 5.1.3.2. Early Pin Planning and I/O Assignment Analysis 5.1.3.3. Pin Features and Connections for HPS Clocks, Reset and PoR 5.1.3.4. Direct to Factory Pin Support for Remote System Update (RSU) Feature 5.1.3.5. Internal Clocks
5.1.4. Reset Configuration x
5.1.4.1. HPS Peripheral Reset Management 5.1.4.2. System Reset Considerations
5.1.7. Design Guidelines for HPS Interfaces x
5.1.7.1. Design Considerations for Selecting PHY Interfaces 5.1.7.2. USB Interface Design Guidelines 5.1.7.3. SD/MMC and eMMC Card Interface Design Guidelines 5.1.7.4. Design Guidelines for Flash Interfaces 5.1.7.5. UART Interface Design Guidelines 5.1.7.6. I2C Interface Design Guidelines
5.1.7.1. Design Considerations for Selecting PHY Interfaces x
5.1.7.1.1. HPS EMAC PHY Interfaces 5.1.7.1.2. RMII and RGMII PHY Interfaces RMII Interface Clocking Scheme GUIDELINE: Consult the Intel Agilex® 7 FPGA Data Sheet for specifics on the choice of REF_CLK source in your application. GUIDELINE: Take into account routing delays and skews on the data and control signals to ensure meeting setup and hold as specified in the HPS SoC Device data sheet and PHY data sheet. GUIDELINE: Ensure the REF_CLK source meets the duty cycle requirement. RGMII I/O Pin Timing Transmit path setup/hold GUIDELINE: For TX_CLK from the Intel Agilex® 7 device, you must introduce 1.8 ns I/O delay to meet the 1.0 ns PHY minimum input setup/hold time in the RGMII spec. Receive path setup/hold GUIDELINE: If the PHY does not support RGMII-ID, use the configurable delay elements in the Intel Agilex® 7 SoC HPS dedicated I/O to center the RX_CLK in the center of the RX_DATA/CTL data valid window. 5.1.7.1.3. PHY Interfaces Connected Through FPGA I/O 5.1.7.1.4. Consider Device Driver Availability 5.1.7.1.5. MDIO 5.1.7.1.6. Signal Integrity
5.1.7.4. Design Guidelines for Flash Interfaces x
5.1.7.4.1. NAND Flash Interface Design Guidelines
5.1.8. Interfacing between the FPGA and HPS x
5.1.8.1. Overview of HPS Memory-Mapped Interfaces 5.1.8.2. Recommended System Topologies 5.1.8.3. Recommended Starting Point for HPS-to-FPGA Interface Designs 5.1.8.4. Information on How to Configure and Use the Bridges
5.1.8.1. Overview of HPS Memory-Mapped Interfaces x
5.1.8.1.1. HPS-to-FPGA Bridge 5.1.8.1.2. Lightweight HPS-to-FPGA Bridge 5.1.8.1.3. FPGA-to-HPS Bridge 5.1.8.1.4. Interface Bandwidths
5.1.8.2. Recommended System Topologies x
5.1.8.2.1. System Level Cache Coherency 5.1.8.2.2. HPS Accesses to FPGA Fabric 5.1.8.2.3. MPU Sharing Data with FPGA 5.1.8.2.4. Examples of Cacheable and Non-Cacheable Data Accesses From the FPGA
5.2. Design Entry for FPGA-only Devices x
5.2.1. Clocking and Reset Design Considerations 5.2.2. I/O and Clock Planning
5.2.2. I/O and Clock Planning x
5.2.2.1. Making FPGA Pin Assignments 5.2.2.2. Early Pin Planning and I/O Assignment Analysis for the FPGA Device 5.2.2.3. I/O Features and Pin Connections 5.2.2.4. Clock and PLL Selection 5.2.2.5. PLL Feature Guidelines 5.2.2.6. Clock Control Features 5.2.2.7. I/O Simultaneous Switching Noise
5.2.2.3. I/O Features and Pin Connections x
5.2.2.3.1. I/O Signaling Type 5.2.2.3.2. Selectable Standards and Flexible I/O Banks 5.2.2.3.3. Dual-Purpose and Special Pin Connections 5.2.2.3.4. Intel Agilex® 7 I/O Features
5.2.2.5. PLL Feature Guidelines x
5.2.2.5.1. Clock Feedback Mode 5.2.2.5.2. Clock Outputs
5.3. Design Entry for NoC x
5.3.1. NoC Architecture Basics 5.3.2. NoC Design Flow 5.3.3. Configuring NoC IP 5.3.4. Instantiating NoC IP 5.3.5. NoC Assignments 5.3.6. NoC Physical Placement 5.3.7. Compilation 5.3.8. Simulation
5.4. EMIF Considerations x
5.4.1. Memory Interfaces 5.4.2. FPGA EMIF Design Considerations
5.5. Nios® Software Processor IP x
5.5.1. Nios® V 5.5.2. Nios® II
6. Board and Software Considerations x
6.1. Early System and Board Planning 6.2. Board Design Guidelines for Intel Agilex® 7 SoC FPGAs 6.3. Pin Connection Considerations for Board Design 6.4. Board Considerations Revision History
6.1. Early System and Board Planning x
6.1.1. SmartVID 6.1.2. Intel® FPGA Power and Thermal Calculator 6.1.3. Thermal Management and Design 6.1.4. Temperature Sensing for Thermal Management 6.1.5. Voltage Sensor 6.1.6. Device Power-Up 6.1.7. Power Pin Connections and Power Supplies 6.1.8. Planning for Device Configuration
6.1.7. Power Pin Connections and Power Supplies x
6.1.7.1. Decoupling Capacitors 6.1.7.2. PLL Board Design Guidelines 6.1.7.3. Transceiver Board Design Guidelines
6.1.8. Planning for Device Configuration x
6.1.8.1. Device Power Cycling and Reconfiguration 6.1.8.2. Configuration Scheme Selection 6.1.8.3. Configuration Features 6.1.8.4. Intel® Quartus® Prime Configuration Settings 6.1.8.5. Configuration Pin Connections
6.1.8.2. Configuration Scheme Selection x
6.1.8.2.1. Serial Configuration Devices 6.1.8.2.2. Intel® FPGA Download Cable
6.1.8.4. Intel® Quartus® Prime Configuration Settings x
6.1.8.4.1. Optional Configuration Pins 6.1.8.4.2. Dual Purpose Configuration Pins
6.1.8.5. Configuration Pin Connections x
6.1.8.5.1. Configuration Pin Voltage Level 6.1.8.5.2. Clock Trace Signal Integrity 6.1.8.5.3. JTAG Pins 6.1.8.5.4. MSEL Configuration Mode Pins 6.1.8.5.5. Other Configuration Pins
6.2. Board Design Guidelines for Intel Agilex® 7 SoC FPGAs x
6.2.1. Boundary Scan for HPS 6.2.2. Embedded Software Debugging and Trace
6.3. Pin Connection Considerations for Board Design x
6.3.1. Board-Related Intel® Quartus® Prime Settings 6.3.2. Signal Integrity Considerations 6.3.3. Board-Level Simulation and Advanced I/O Timing Analysis
6.3.1. Board-Related Intel® Quartus® Prime Settings x
6.3.1.1. Unused Pins
6.3.2. Signal Integrity Considerations x
6.3.2.1. High-Speed Board Design 6.3.2.2. Voltage Reference Pins 6.3.2.3. Simultaneous Switching Noise 6.3.2.4. I/O Termination
7. Design Implementation, Analysis, Optimization, and Verification x
7.1. Selecting a Synthesis Tool 7.2. Device Resource Utilization Reports 7.3. Intel® Quartus® Prime Messages 7.4. Timing Constraints and Analysis 7.5. Area and Timing Optimization 7.6. Preserving Performance and Reducing Compilation Time 7.7. Designing with Intel® Hyperflex™ 7.8. Simulation 7.9. Power Analysis 7.10. Power Optimization 7.11. Design Implementation, Analysis, Optimization, and Verification Revision History
7.4. Timing Constraints and Analysis x
7.4.1. Recommended Timing Optimization and Analysis Assignments
7.10. Power Optimization x
7.10.1. Device and Design Power Optimization Techniques 7.10.2. Intel® Quartus® Prime Power Optimization Techniques
7.10.1. Device and Design Power Optimization Techniques x
7.10.1.1. Device Speed Grade 7.10.1.2. Clock Power Management 7.10.1.3. Memory Power Reduction 7.10.1.4. I/O Power Guidelines
8. Debugging x
8.1. On-Chip Debug Overview 8.2. On-Chip Debugging Tools 8.3. Debugging Revision History
8.1. On-Chip Debug Overview x
8.1.1. Planning Guidelines for Debugging Tools
9. Embedded Software Design Guidelines for Intel Agilex® 7 SoC FPGAs x
9.1. Overview 9.2. Golden Hardware Reference Design (GHRD) 9.3. Define Software Requirements 9.4. Define Software Architecture 9.5. Selecting Software Tools 9.6. Choosing the Bootloader Software 9.7. Selecting an Operating System for Your Application 9.8. Assembling Your Software Development Platform for Linux* 9.9. Assembling your Software Development Platform for Partner OS or RTOS 9.10. Driver Considerations 9.11. Boot And Configuration Considerations 9.12. System Reset Considerations 9.13. Flash Considerations 9.14. Develop Application 9.15. Test and Validate 9.16. Embedded Software Design Guidelines Revision History
9.5. Selecting Software Tools x
9.5.1. Selecting Software Build Tools 9.5.2. Selecting Software Debug Tools 9.5.3. Selecting Software Trace Tools
9.7. Selecting an Operating System for Your Application x
9.7.1. Using Linux* or RTOS 9.7.2. Using the Bootloader as a Bare-Metal Framework 9.7.3. Using Symmetrical vs. Asymmetrical Multiprocessing (SMP vs. AMP) Modes
9.8. Assembling Your Software Development Platform for Linux* x
9.8.1. Golden System Reference Design (GSRD) for Linux* 9.8.2. Source Code Management Considerations
9.11. Boot And Configuration Considerations x
9.11.1. Configuration Sources 9.11.2. Configuration Flash 9.11.3. Configuration Clock 9.11.4. Selecting HPS Boot Options 9.11.5. HPS Boot Sources 9.11.6. Remote System Update (RSU)
9.13. Flash Considerations x
9.13.1. Flash Programming Method 9.13.2. Using a Single flash for Both FPGA Configuration and HPS Mass Storage
1. Introduction to the Intel Agilex® 7 Device Design Guidelines
2. System Specification
3. Device Selection
4. Security Considerations
5. Design Entry
6. Board and Software Considerations
7. Design Implementation, Analysis, Optimization, and Verification
8. Debugging
9. Embedded Software Design Guidelines for Intel Agilex® 7 SoC FPGAs

5.1.7.1.2. RMII and RGMII PHY Interfaces

Determine whether to use RMII or RGMII PHY Interfaces.

RMII

RMII uses a single centralized system-synchronous 50 MHz clock source (REF_CLK) for both transmit and receive paths across all ports. This simplifies system clocking and lowers pin counts in high port density systems, because your design can use a single board oscillator as opposed to per port TX_CLK/RX_CLK source synchronous clock pairs.

RMII uses two-bit wide transmit and receive data paths. All data and control signals are synchronous to the REF_CLK rising edge. The RX_ER control signal is not used. In 10Mbps mode, all data and control signals are held valid for 10 REF_CLK clock cycles.

Figure 2. RMII MAC/PHY Interface

Interface Clocking Scheme

EMACs and RMII PHYs can provide the 50 MHz REF_CLK source. Using clock resources already present such as HPS_OSC_CLK input, internal PLLs further simplifies system clocking design and eliminates the need for an additional clock source.

This section discusses system design scenarios for both HPS EMAC-sourced and PHY-sourced REF_CLK.

GUIDELINE: Consult the Intel Agilex® 7 FPGA Data Sheet for specifics on the choice of REF_CLK source in your application.

Note: Make sure your choice of PHY supports the REF_CLK clocking scheme in your application. Note any requirements and usage considerations specified in the Intel Agilex® 7 FPGA Data Sheet.
You can use one of the following two methods for sourcing REF_CLK:
  • HPS-Sourced REF_CLK
  • PHY-Sourced REF_CLK
Figure 3. HPS Sourced REF_CLKIn this scheme, connect the EMAC’s HPS RMII I/O TX_CLK output to both the HPS RMII I/O RX_CLK and PHY REF_CLK inputs.
Figure 4. PHY Sourced REF_CLKIn this scheme, connect the PHY’s REF_CLK output to the EMAC’s HPS RMII I/O RX_CLK input. Leave the EMAC’s HPS RMII I/O TX_CLK output unconnected. PHYs capable of sourcing REF_CLK are typically configured to do so through pin bootstrapping and require an external crystal or clock input to generate REF_CLK.

If RX_CLK is routed daisy-chain from source to MAC to PHY or source to PHY, you must account for the flight time difference as both REF_CLK loads observes the clock at different times.

GUIDELINE: Take into account routing delays and skews on the data and control signals to ensure meeting setup and hold as specified in the HPS SoC Device data sheet and PHY data sheet.

Signal length matching is not necessary unless you have signal lengths in excess of 24 inches, in which case you must perform some basic timing analysis with clock delays versus data delays.

The period is 20 ns with the 50 MHz REF_CLK and remains at this frequency regardless of whether the PHY is set to 10Mbps or 100Mbps mode.

All clocking in the HPS EMAC is based on the RX_CLK, so the Tco and PCB flight time of REF_CLK from either the EMAC or PHY can be ignored. Typical board traces up to 12 inches yield only 2 ns of flight time and Tsu of RXD to RX_CLK is 4 ns minimum, well under the 20 ns period.

There is a 2 ns hold requirement of RXD versus RX_CLK which is easily satisfied as well because the Tco of TXD with respect to RX_CLK for either the MAC or the PHY is typically over 2 ns. For the Intel Agilex® 7 SoC device, the Tco of TXD with respect to RX_CLK is 2 ns to 10 ns.

GUIDELINE: Ensure the REF_CLK source meets the duty cycle requirement.

There is no jitter specification for the REF_CLK, but there is a duty cycle requirement of 35 to 65 percent. This requirement is met by the Intel Agilex® 7 SoC device PLLs and clock outputs for GPIO or for the TX_CLK signal coming from the HPS IP specifically.

RGMII

RGMII is the most common interface because it supports 10 Mbps, 100 Mbps, and 1000 Mbps connection speeds at the PHY layer.

RGMII uses four-bit wide transmit and receive data paths, each with its own source-synchronous clock. All transmit data and control signals are source synchronous to TX_CLK, and all receive data and control signals are source synchronous to RX_CLK.

For all speed modes, TX_CLK is sourced by the MAC, and RX_CLK is sourced by the PHY. In 1000 Mbps mode, TX_CLK and RX_CLK are 125 MHz, and Dual Data Rate (DDR) signaling is used. In 10 Mbps and 100 Mbps modes, TX_CLK and RX_CLK are 2.5 MHz and 25 MHz, respectively, and rising edge Single Data Rate (SDR) signaling is used.

Figure 5. RGMII MAC/PHY Interface

I/O Pin Timing

This section addresses RGMII interface timing from the perspective of meeting requirements in the 1000 Mbps mode. The interface timing margins are most demanding in 1000 Mbps mode, thus it is the only scenario you consider here.

At 125 MHz, the period is 8 ns, but because both edges are used, the effective period is only 4 ns. The TX and RX busses are separate and source synchronous, simplifying timing. The RGMII specification calls for CLK to be delayed from DATA at the receiver in either direction by a minimum 1.0 ns and a maximum 2.6 ns.

In other words, the TX_CLK must be delayed from the MAC output to the PHY input and the RX_CLK from the PHY output to the MAC input. The signals are transmitted source synchronously within the +/- 500 ps RGMII skew specification in each direction as measured at the output pins. The minimum delay needed in each direction is 1 ns but Intel® recommends to target a delay of 1.5 ns to 2.0 ns to ensure significant timing margin.

Transmit path setup/hold

Only setup and hold for TX_CLK to TX_CTL and TXD[3:0] matter for transmit. The Intel Agilex® 7 HPS I/O can provide up to ~3 ns additional delay on outputs in ~100 ps increments. For specific values, refer to the Intel Agilex® 7 FPGA Data Sheet. The delay added to the EMAC's TX_CLK output when using HPS dedicated I/O can be configured in the HPS Platform Designer IP component I/O Delays parameter.

GUIDELINE: For TX_CLK from the Intel Agilex® 7 device, you must introduce 1.8 ns I/O delay to meet the 1.0 ns PHY minimum input setup/hold time in the RGMII spec.

Receive path setup/hold

Only setup and hold for RX_CLK to RX_CTL and RXD[3:0] are necessary to consider for receive timings. The Intel Agilex® 7 HPS I/O can provide up to ~3 ns additional delay on inputs. For specific values, refer to the Intel Agilex® 7 FPGA Data Sheet. For Intel Agilex® 7 device inputs, the up to 2.25 ns I/O delay can achieve this timing for RX_CLK without any other considerations on the PHY side or board trace delay side. The delay added to the EMAC's RX_CLK output when using HPS dedicated I/O can be configured in the HPS Platform Designer IP component I/O Delays parameter.

GUIDELINE: If the PHY does not support RGMII-ID, use the configurable delay elements in the Intel Agilex® 7 SoC HPS dedicated I/O to center the RX_CLK in the center of the RX_DATA/CTL data valid window.

Related Information
3 This value is pending characterization.
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